Shift Register (TCPWM)

group group_tcpwm_shiftreg

Driver API for Shift Register.

The functions and other declarations used in this part of the driver are in cy_tcpwm_shiftreg.h. You can also include cy_pdl.h to get access to all functions and declarations in the PDL.

Shift Register functionality shifts the counter value to the right. A shift register is used to apply a signal delay function which can be used eg: in detecting frequency shift keying (FSK) signals. A shift register is also used in parallel-in to serial-out data conversion and serial-in to parallel-out data conversion.


  • 16- or 32-bit Counter

  • 2 compare (CC0/CC1) registers with double buffer.

  • Programmable Counter taps through PERIOD_BUFF register.

  • Line output generated from a XOR combination of all enabled counter taps (bit position) defined by PERIOD_BUFF.

  • Programmable Compare Register. Compare value can be swapped with a buffered compare value on comparison event.

  • Interrupt on Comparision match events (CC0_MATCH/CC1_MATCH).

  • Start, Reload, Stop, Shift, and Serail-in Inputs.

  • Comparision match and Line Outputs.

  • Line output can be output with invert polarity.


Shift Register mode is available only in TCPWM Version 2

Configuration Considerations

The Shift Register configuration can be divided to number of sequential steps listed below:

  • Configure Shift Register

  • Assign and Configure Pins

  • Assign Clock Divider

  • Enable Shift Register

  • Start Shift Register

Configure Shift Register

To configure Shift Register, provide the configuration parameters in the cy_stc_tcpwm_shiftreg_config_t structure. The configuration structure can be modified through software, but if the configurator in ModusToolbox is used then the configuration structure will be updated with the users inputs. To initialize the driver, call Cy_TCPWM_ShiftReg_Init function providing a pointer to the populated cy_stc_tcpwm_shiftreg_config_t structure.

    /* Scenario: Initialize the first (index = 0) of TCPWM 0 block
     * as Shift Register with configuration settings
    cy_stc_tcpwm_shiftreg_config_t shiftreg_config =
       /* .clockPrescaler       = */CY_TCPWM_SHIFTREG_PRESCALER_DIVBY_1,
       /* .tapsEnabled          = */0x80000000UL,
       /* .compare0             = */16384UL,
       /* .compareBuf0          = */16384UL,
       /* .enableCompare0Swap   = */false,
       /* .compare1             = */16384UL,
       /* .compareBuf1          = */16384UL,
       /* .enableCompare1Swap   = */false,
       /* .interruptSources     = */CY_TCPWM_INT_ON_CC0,                /* Interrupt will rise on CC0 Match*/
       /* .invertShiftRegOut    = */CY_TCPWM_SHIFTREG_INVERT_DISABLE,   /* Not inverted */
       /* .invertShiftRegOutN   = */CY_TCPWM_SHIFTREG_INVERT_DISABLE,   /* Not inverted */
       /* .reloadInputMode      = */CY_TCPWM_INPUT_LEVEL,               /* This input is NOT used, leave it in default state (CY_TCPWM_INPUT_LEVEL) */
       /* .reloadInput          = */CY_TCPWM_INPUT_0,
       /* .startInputMode       = */CY_TCPWM_INPUT_LEVEL,               /* This input is NOT used, leave it in default state (CY_TCPWM_INPUT_LEVEL) */
       /* .startInput           = */CY_TCPWM_INPUT_0,
       /* .killInputMode        = */CY_TCPWM_INPUT_LEVEL,               /* This input is NOT used, leave it in default state (CY_TCPWM_INPUT_LEVEL) */
       /* .killInput            = */CY_TCPWM_INPUT_0,
       /* .shiftInputMode       = */CY_TCPWM_INPUT_LEVEL,               /* Set this input to LEVEL and 1 (high logic level) */
       /* .shiftInput           = */CY_TCPWM_INPUT_1,                   /* Shift Register will run forever */
       /* .serialInputMode      = */CY_TCPWM_INPUT_LEVEL,               /* This input is NOT used, leave it in default state (CY_TCPWM_INPUT_LEVEL) */
       /* .serialInput          = */CY_TCPWM_INPUT_0,
       /* .shiftRegOnDisable    = */CY_TCPWM_SHIFTREG_OUTPUT_HIGHZ,     /* Default High impedance mode*/
       /* .trigger0Event        = */CY_TCPWM_CNT_TRIGGER_ON_DISABLED,   /* Disable output trigger0 event generation*/
       /* .trigger1Event        = */CY_TCPWM_CNT_TRIGGER_ON_DISABLED,   /* Disable output trigger1 event generation*/

    #define MY_TCPWM_SHIFTREG_NUM   (0UL)

    if (CY_TCPWM_SUCCESS != Cy_TCPWM_ShiftReg_Init(TCPWM0, MY_TCPWM_SHIFTREG_NUM, &shiftreg_config))
        /* Handle possible errors */

Assign and Configure Pins

The dedicated TCPWM pins can be used. The HSIOM register must be configured to connect the block to the pins. Use the GPIO (General Purpose Input Output) driver API to do that.

    /* Scenario: 
     * Configure P0[4] as Shift Register Line Output.
     * Configure P0[5] as Shift Register Line Compliment Output.

Assign Clock Divider

The clock source must be connected for proper operation. Any of the peripheral clock dividers could be used. Use the SysClk (System Clock) driver API to do that.

    /* Scenario: Assign the first 8-bit peripheral clock divider with
     * divide ratio = 100 to TCPWM0 block:

    Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM0_CLOCKS0, CY_SYSCLK_DIV_8_BIT, 0UL);
    Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0UL, 99UL);
    Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0UL);

Enable Shift Register

Shift Register has to be enabled before starting

    /* Scenario: Enable Shift Register */
    #define MY_TCPWM_SHIFTREG_NUM   (0UL)


Start Shift Register

To start Shift Register operation Cy_TCPWM_TriggerStart_Single API can be used.

    /* Scenario: Use software trigger to start Shift Register operation */
    #define MY_TCPWM_SHIFTREG_NUM   (0UL)

    Cy_TCPWM_TriggerStart_Single(TCPWM0, MY_TCPWM_SHIFTREG_NUM);