TCPWM (Timer Counter PWM)

group group_tcpwm

The TCPWM driver is a multifunction driver that implements Timer Counter, PWM, Quadrature Decoder and Shift Register functionality using the TCPWM block.

The functions and other declarations used in this driver are in cy_tcpwm_counter.h, cy_tcpwm_pwm.h, cy_tcpwm_quaddec.h, cy_tcpwm_shiftreg.h respectively. Include cy_pdl.h to get access to all functions and declarations in the PDL.

Each TCPWM block is a collection of counters that can all be triggered simultaneously. For each function call, the base register address of the TCPWM being used must be passed first, followed by the index of the counter you want to touch next.

The TCPWM supports seven function modes:

  • Timer

  • Capture

  • Quadrature Decoder

  • Pulse Width Modulation (PWM)

  • PWM with dead time insertion (PWMDT)

  • Pseudo random PWM (PWMPR)

  • Shift Register

The TCPWM driver is structured to map these seven fuctional modes to four high level operating modes:

  • Timer/Counter (includes Timer, Capture modes)


  • Quadrature Decoder

  • Shift Register

A brief description on each of the operating modes:


Use this mode whenever a specific timing interval or measurement is needed. Examples include:

  • Creating a periodic interrupt for running other system tasks

  • Measuring frequency of an input signal

  • Measuring pulse width of an input signal

  • Measuring time between two external events

  • Counting events

  • Triggering other system resources after x number events

  • Capturing time stamps when events occur


Use this mode when an output square wave is needed with a specific period and duty cycle, such as:

  • Creating arbitrary square wave outputs

  • Driving an LED (changing the brightness)

  • Driving Motors (dead time assertion available)

Quadrature Decoder

A quadrature decoder is used to decode the output of a quadrature encoder. A quadrature encoder senses the position, velocity, and direction of an object (for example a rotating axle, or a spinning mouse ball). A quadrature decoder can also be used for precision measurement of speed, acceleration, and position of a motor’s rotor, or with a rotary switch to determine user input. Shift Register

Shift Register functionality shifts the counter value to the right. A shift register is used to apply a signal delay function which can be used eg: in detecting frequency shift keying (FSK) signals. A shift register is also used in parallel-in to serial-out data conversion and serial-in to parallel-out data conversion.

TCPWM Versions

There are two versions of TCPWM driver

TCPWM Version 2

  • Devices CY8C61x4 and CY8C62x4 use this version.

  • Supports up to four counter groups (check TRM for actual number of groups supported)

  • Each counter group consists of up to 256 counters (check TRM for actual number of counters supported)

  • Each counter

    • Can run in one of seven function modes

    • Supports various counting modes:

      • One-shot mode, Continuous mode (Up/Down/Up-down)

    • Selects input signals

      • Start, Reload, Stop, Count, and two Capture event signals

    • Generates output signals:

      • Two output triggers, PWM output, and Interrupt

    • Trigger Outputs (TR_OUT0/1) and an Interrupt on an event

      • Overflow (OV)

      • Underflow (UN)

      • Terminal Count (TC)

      • CC0/1_MATCH

      • LINE_OUT

    • Supports debug mode

    • Each counter can produce two output signals


  • Input Trigger Selection and Event Detection

    • The counter control signals are generated as follows:

      • Selects input signals from two types of trigger multiplexer signals

        • Group trigger and one-to-one trigger

        • The constant ‘1’ and ‘0’ are also used as input triggers

      • Detects the selected edge from four types

        • Rising edge/falling edge/any edge/no edge

      • Supports software (SW) command

        • SW command of Trigger Multiplexer/SW command of TCPWM


  • Simultaneous Activation:

    • When a Trigger Multiplexer block SW command is used, the TCPWM counters can be activated at the same time


TCPWM Version 1

  • Devices CY8C61x6, CY8C61x7, CY8C62x5, CY8C62x6, CY8C62x7, CY8C62x8, CY8C62xA, CY8C63x6, CY8C63x7, CYS0644xxZI-S2D44, CYB0644xxZI-S4D44, CYB06447BZI-BLDX, CYB06447BZI-D54 and CYB06445LQI-S3D42 use this version.

  • Supports up to 32 counters (check TRM for actual number of counters supported)

  • Synchronized operation of multiple counters.

  • 16 or 32 bit counter, compare/capture (CC) and period registers.

  • CC and period registers are double buffered.

  • Up, down and up/down counting modes.

  • 14 trigger input signals and 2 constant input signals: ‘0’ and ‘1’, for a total of 16 hardware (HW) input signals

  • Rising edge, falling edge, combined rising/falling edge detection or pass-through on all HW input signals to derive counter events.

  • The start, reload, stop and capture events can be generated by software.

  • Clock pre-scaling (1x, 2x, 4x … 128x).

  • Support Pseudo Random PWM

  • 3 output trigger signals for each counter to indicate underflow, overflow and cc_match events.

  • 2 PWM complementary output lines for each counter. Dead time insertion ([0, 255] counter cycles).

  • Support one interrupt output for each counter.


  • Many functions work with an individual counter. You can also manage multiple counters simultaneously for certain functions.

  • These are listed in the Functions section of the TCPWM.

  • You can enable, disable, or trigger (in various ways) multiple counters simultaneously.

  • For these functions you provide a bit field representing each counter in the TCPWM you want to control.

  • You can represent the bit field as an ORed mask of each counter, like ((1U << cntNumX) | (1U << cntNumX) | (1U << cntNumX)), where X is the counter number from 0 to 31.


More Information

For more information on the TCPWM peripheral, refer to the technical reference manual (TRM).




Reason for Change


Added new option to Swap Overflow/Underflow behavior in PWM Centre/Asymmetric Alignment modes.

New feature.


Added new features: Shift Register, New QuadDec modes, Additional Compare/Capture Buffer.

New silicon family support.


Minor documentation updates.

Documentation enhancement.


Added header guards CY_IP_MXTCPWM.

To enable the PDL compilation with wounded out IP blocks.


Flattened the organization of the driver source code into the single source directory and the single include directory.

Driver library directory-structure simplification.

Added register access layer. Use register access macros instead of direct register access using dereferenced pointers.

Makes register access device-independent, so that the PDL does not need to be recompiled for each supported part number.


Added a deviation to the MISRA Compliance section. Added function-level code snippets.

Documentation update and clarification


Initial version