SD Host Events¶
Each event is encoded in a separate bit, and therefore it is possible to notify about multiple events.
In SD/eMMC mode, this event is set after detecting the end bit of a response except for Auto CMD12 and Auto CMD23. This event is not generated when the Response Interrupt is disabled.
This event is set when a read/write transfer and a command with the Busy Status are completed.
This event is set when both read/write transactions are stopped at the block gap due to a Stop-at-Block-Gap Request.
This event is set if the Host Controller detects a SDMA Buffer Boundary during a transfer. For ADMA, the Host controller generates this interrupt by setting the Int field in the descriptor table. This interrupt is not generated after a Transfer Complete.
The Buffer Write is ready.
This event is set if the Buffer Write Enable changes from 0 to 1.
The Buffer Read is ready.
This event is set if the Buffer Read Enable changes from 0 to 1.
This event is set if the Card Inserted in the Present State register changes from 0 to 1.
This event is set if the Card Inserted in the Present State register changes from 1 to 0.
The Card interrupt.
This event reflects the synchronized value of DAT Interrupt Input for SD Mode
This status is set when R of the response register is set to 1 and Response Type R1/R5 is set to 0 in the Transfer Mode register. This interrupt is used with the response check function.
Command Queuing event.
This status is set if a Command Queuing/Crypto related event has occurred in eMMC/SD mode.
If any of the bits in the Error Interrupt Status register are set, then this bit is set.
Command timeout error.
In SD/eMMC Mode, this event is set only if no response is returned within 64 SD clock cycles from the end bit of the command. If the Host Controller detects a CMD line conflict, along with Command CRC Error bit, this event is set to 1, without waiting for 64 SD/eMMC card clock cycles.
Command CRC error.
A Command CRC Error is generated in SD/eMMC mode when:
A response is returned and the Command Timeout Error is set to 0 (indicating no timeout), this bit is set to 1 when detecting a CRC error in the command response.
The Host Controller detects a CMD line conflict by monitoring the CMD line when a command is issued. If the Host Controller drives the CMD line to level 1, but detects level 0 on the CMD line at the next SD clock edge, then the Host Controller aborts the command (stop driving CMD line) and sets this bit to 1. The Command Timeout Error is also set to 1 to distinguish a CMD line conflict.
Command End Bit error.
This bit is set after detecting that the end bit of a command response is 0 in SD/eMMC mode.
Command Index error.
This bit is set if a Command Index error occurs in the command response in SD/eMMC mode.
Data Timeout error.
This bit is set in SD/eMMC mode when detecting one of the following timeout conditions:
Busy timeout for R1b, R5b type
Busy timeout after Write CRC status
Write CRC Status timeout
Read Data timeout.
Data CRC error.
This error occurs in SD/eMMC mode after detecting a CRC error while transferring read data that uses the DAT line, after detecting the Write CRC status having a value other than 010 or when writing a CRC status timeout.
Data End Bit error.
This error occurs in SD/eMMC mode either when detecting 0 at the end bit position of read data that uses the DAT line or at the end bit position of the CRC status.
Current Limit error.
The SD Host driver does not support this function, this bit is always set to 0.
Auto CMD error.
This error status is used by Auto CMD12 and Auto CMD23 in SD/eMMC mode. This bit is set after detecting that any of the bits D00 to D05 in the Auto CMD Error Status register has changed from 0 to 1. D07 is effective in case for Auto CMD12. The Auto CMD Error Status register is valid while this bit is set to 1 and may be cleared by clearing this bit.
This bit is set when the Host Controller detects an error during an ADMA-based data transfer. The possible reasons for an error:
An error response is received from the System bus;
ADMA3, ADMA2 Descriptors are invalid;
CQE Task or Transfer descriptors are invalid. When an error occurs, the state of the ADMA is saved in the ADMA Error Status register.
The SD Host driver does not support this function.
Host Controller Version 4.00 supports the response error check function to avoid overhead of the response error check by Host Driver during DMA execution. If the Response Error Check Enable is set to 1 in the Transfer Mode register, the Host Controller checks R1 or R5 response. If an error is detected in a response, this bit is set to 1. This is applicable in SD/eMMC mode.
Boot Acknowledgement error.
This bit is set when there is a timeout for boot acknowledgement or after detecting the boot ACK status having a value other than 010. This is applicable only when boot acknowledgement is expected in eMMC mode.