Functions¶

group group_pra_functions

Functions

void Cy_PRA_Init(void)

Initializes the PRA driver:

Initializes the register access array with the register addresses (Cortex-M0+)
Sets up the IPC communication between CPU cores
Checks that the driver versions match on the Cortex-M0+ and Cortex-M4 sides.

Call the function before accessing any protected registers. It is called during a device startup from SystemInit().

cy_en_pra_status_t Cy_PRA_SendCmd(uint16_t cmd, uint16_t regIndex, uint32_t clearMask, uint32_t setMask)

Takes the parameters, passes them to the secure Cortex-M0+ via IPC, waits for Cortex-M0+ to finish and reports the status.

Parameters

cmd – The command to execute on the secure side. The macros for this parameter are defined in the cy_pra.h file with the CY_PRA_MSG_TYPE_ prefix.
regIndex – The index of the function or register depending on the command parameter. The macros for this parameter are defined in the cy_pra.h file with the CY_PRA_INDX_ prefix.
clearMask – Data sent to secure the core.
setMask – Additional data send to secure the core.

Returns

The command execution status. For the register read command, the read value is returned.

cy_en_pra_pin_prot_type_t Cy_PRA_GetPinProtType(GPIO_PRT_Type *base, uint32_t pinNum): Find the matching PORT and PIN number from External clock secure PIN list and returns protection status of the PIN.

bool Cy_PRA_IsPortSecure(GPIO_PRT_Type *base): Find the matching PORT from External clock secure PIN list and returns protection status of the PORT.

uint16_t Cy_PRA_GetPortRegIndex(GPIO_PRT_Type *base, uint16_t subIndex): Find the matching PORT and PIN number from External clock secure PIN list and returns port address index.

uint16_t Cy_PRA_GetHsiomRegIndex(GPIO_PRT_Type *base, uint16_t subIndex): Find the matching PORT address from External clock secure PIN list and returns HSIOM port address index.

cy_en_pra_status_t Cy_PRA_SystemConfig(const cy_stc_pra_system_config_t *devConfig)

Validates cy_stc_pra_system_config_t and applies the provided settings.

Function Usage

    /* Scenario: there is a need to be done in case then PDL is used
     * in standalone mode without Board Support Packages
     * (that uses Device Configurator utility to provide
     * GeneratedSource folder for the initial configuration
     * of the device).
     */
    cy_en_pra_status_t status = CY_PRA_STATUS_INVALID_PARAM;

    cy_stc_pra_system_config_t sysConfig =
    {
        .powerEnable=true,
        .ldoEnable=true,
        .pmicEnable=false,
        .vBackupVDDDEnable=true,
        .ulpEnable=false,
        .ecoEnable=false,
        .extClkEnable=false,
        .iloEnable=true,
        .wcoEnable=false,
        .fllEnable=false,
        .pll0Enable=false,
        .pll1Enable=false,
        .path0Enable=true,
        .path1Enable=false,
        .path2Enable=false,
        .path3Enable=false,
        .path4Enable=false,
        .path5Enable=false,
        .clkFastEnable=true,
        .clkPeriEnable=true,
        .clkSlowEnable=true,
        .clkHF0Enable=true,
        .clkHF1Enable=false,
        .clkHF2Enable=false,
        .clkHF3Enable=false,
        .clkHF4Enable=false,
        .clkHF5Enable=false,
        .clkPumpEnable=false,
        .clkLFEnable=true,
        .clkBakEnable=false,
        .clkTimerEnable=false,
        .clkAltSysTickEnable=false,
        .piloEnable=false,
        .clkAltHfEnable=false,
        .ldoVoltage=(cy_en_syspm_ldo_voltage_t)CY_SYSPM_LDO_VOLTAGE_LP,
        .buckVoltage=(cy_en_syspm_buck_voltage1_t)0,
        .pwrCurrentModeMin=false,
        .ecoFreqHz=0,
        .ecoLoad=0,
        .ecoEsr=0,
        .ecoDriveLevel=0,
        .ecoInPort=(GPIO_PRT_Type *)0x0,
        .ecoOutPort=(GPIO_PRT_Type *)0x0,
        .ecoInPinNum=0,
        .ecoOutPinNum=0,
        .extClkFreqHz=0,
        .extClkPort=(GPIO_PRT_Type *)0x0,
        .extClkPinNum=0,
        .extClkHsiom=(en_hsiom_sel_t)HSIOM_SEL_GPIO,
        .iloHibernateON=true,
        .bypassEnable=false,
        .wcoInPort=(GPIO_PRT_Type *)0x0,
        .wcoOutPort=(GPIO_PRT_Type *)0x0,
        .wcoInPinNum=0,
        .wcoOutPinNum=0,
        .fllOutFreqHz=0,
        .fllMult=0,
        .fllRefDiv=0,
        .fllCcoRange=(cy_en_fll_cco_ranges_t)CY_SYSCLK_FLL_CCO_RANGE0,
        .enableOutputDiv=false,
        .lockTolerance=0,
        .igain=0,
        .pgain=0,
        .settlingCount=0,
        .outputMode=(cy_en_fll_pll_output_mode_t)CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
        .ccoFreq=0,
        .pll0OutFreqHz=0,
        .pll0FeedbackDiv=0,
        .pll0ReferenceDiv=0,
        .pll0OutputDiv=0,
        .pll0LfMode=false,
        .pll0OutputMode=(cy_en_fll_pll_output_mode_t)CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
        .pll1OutFreqHz=0,
        .pll1FeedbackDiv=0,
        .pll1ReferenceDiv=0,
        .pll1OutputDiv=0,
        .pll1LfMode=false,
        .pll1OutputMode=(cy_en_fll_pll_output_mode_t)CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
        .path0Src=(cy_en_clkpath_in_sources_t)CY_SYSCLK_CLKPATH_IN_IMO,
        .path1Src=(cy_en_clkpath_in_sources_t)CY_SYSCLK_CLKPATH_IN_IMO,
        .path2Src=(cy_en_clkpath_in_sources_t)CY_SYSCLK_CLKPATH_IN_IMO,
        .path3Src=(cy_en_clkpath_in_sources_t)CY_SYSCLK_CLKPATH_IN_IMO,
        .path4Src=(cy_en_clkpath_in_sources_t)CY_SYSCLK_CLKPATH_IN_IMO,
        .path5Src=(cy_en_clkpath_in_sources_t)CY_SYSCLK_CLKPATH_IN_IMO,
        .clkFastDiv=0,
        .clkPeriDiv=0,
        .clkSlowDiv=0,
        .hf0Source=(cy_en_clkhf_in_sources_t)CY_SYSCLK_CLKHF_IN_CLKPATH0,
        .hf0Divider=(cy_en_clkhf_dividers_t)CY_SYSCLK_CLKHF_NO_DIVIDE,
        .hf0OutFreqMHz=8,
        .hf1Source=(cy_en_clkhf_in_sources_t)CY_SYSCLK_CLKHF_IN_CLKPATH0,
        .hf1Divider=(cy_en_clkhf_dividers_t)CY_SYSCLK_CLKHF_NO_DIVIDE,
        .hf1OutFreqMHz=0,
        .hf2Source=(cy_en_clkhf_in_sources_t)CY_SYSCLK_CLKHF_IN_CLKPATH0,
        .hf2Divider=(cy_en_clkhf_dividers_t)CY_SYSCLK_CLKHF_NO_DIVIDE,
        .hf2OutFreqMHz=0,
        .hf3Source=(cy_en_clkhf_in_sources_t)CY_SYSCLK_CLKHF_IN_CLKPATH0,
        .hf3Divider=(cy_en_clkhf_dividers_t)CY_SYSCLK_CLKHF_NO_DIVIDE,
        .hf3OutFreqMHz=0,
        .hf4Source=(cy_en_clkhf_in_sources_t)CY_SYSCLK_CLKHF_IN_CLKPATH0,
        .hf4Divider=(cy_en_clkhf_dividers_t)CY_SYSCLK_CLKHF_NO_DIVIDE,
        .hf4OutFreqMHz=0,
        .hf5Source=(cy_en_clkhf_in_sources_t)CY_SYSCLK_CLKHF_IN_CLKPATH0,
        .hf5Divider=(cy_en_clkhf_dividers_t)CY_SYSCLK_CLKHF_NO_DIVIDE,
        .hf5OutFreqMHz=0,
        .pumpSource=(cy_en_clkpump_in_sources_t)CY_SYSCLK_PUMP_IN_CLKPATH0,
        .pumpDivider=(cy_en_clkpump_divide_t)CY_SYSCLK_PUMP_NO_DIV,
        .clkLfSource=(cy_en_clklf_in_sources_t)CY_SYSCLK_CLKLF_IN_ILO,
        .clkBakSource=(cy_en_clkbak_in_sources_t)CY_SYSCLK_BAK_IN_WCO,
        .clkTimerSource=(cy_en_clktimer_in_sources_t)CY_SYSCLK_CLKTIMER_IN_IMO,
        .clkTimerDivider=0,
        .clkSrcAltSysTick =(cy_en_systick_clock_source_t)CY_SYSTICK_CLOCK_SOURCE_CLK_LF,
        .altHFcLoad=0,
        .altHFxtalStartUpTime=0,
        .altHFclkFreq=0,
        .altHFsysClkDiv=0,
        .altHFvoltageReg=0
    };

    status = CY_PRA_FUNCTION_CALL_RETURN_PARAM(CY_PRA_MSG_TYPE_SYS_CFG_FUNC,
                                               CY_PRA_FUNC_INIT_CYCFG_DEVICE,
                                               &sysConfig);

Parameters: devConfig – The device configuration structure initialized with Device Configurator.
Returns: cy_en_pra_status_t