Bit 0: Less entries in the TX FIFO than specified by Trigger Level.
Bit 1: TX FIFO is not full.
Bit 4: TX FIFO is empty, i.e.
it has 0 entries.
Bit 5: Attempt to write to a full TX FIFO.
Bit 6: Attempt to read from an empty TX FIFO.
This happens when the IP is ready to transfer data and TX_EMPTY is ‘1’.
Bit 8: Tx watchdog event occurs.
Bit 16: More entries in the RX FIFO than specified by Trigger Level.
Bit 18: RX FIFO is not empty.
Bit 19: RX FIFO is full.
Bit 21: Attempt to write to a full RX FIFO.
Bit 22: Attempt to read from an empty RX FIFO.
Bit 24: Rx watchdog event occurs.