Data Structures¶
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group
group_i2s_data_structures -
struct
I2S_Type¶ - #include <>
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struct
cy_stc_i2s_config_t - #include <>
I2S initialization configuration.
Public Members
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bool
txEnabled Enables the I2S TX component: ‘false’: disabled.
‘true’: enabled.
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bool
rxEnabled Enables the I2S RX component: ‘false’: disabled.
‘true’: enabled.
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bool
txDmaTrigger ‘false’: TX DMA trigger disabled, ‘true’: TX DMA trigger enabled.
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bool
rxDmaTrigger ‘false’: RX DMA trigger disabled, ‘true’: RX DMA trigger enabled.
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uint8_t
clkDiv CLK_SEL divider: 1: Bypass, 2: 1/2, 3: 1/3, …, 64: 1/64.
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bool
extClk ‘false’: internal clock, ‘true’: external clock.
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bool
txMasterMode ‘false’: TX in slave mode, ‘true’: TX in master mode.
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cy_en_i2s_alignment_t
txAlignment TX data alignment, see: cy_en_i2s_alignment_t.
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cy_en_i2s_ws_pw_t
txWsPulseWidth TX Word Select pulse width.
The value of this parameter is ignored in I2S and Left Justified modes the WS pulse width is always “one channel length” in these modes.
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bool
txWatchdogEnable ‘false’: TX watchdog disabled, ‘true’: TX watchdog enabled.
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uint32_t
txWatchdogValue TX watchdog counter value (32 bit).
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bool
txSdoLatchingTime ‘false’: SDO bit starts at falling edge (accordingly to the I2S Standard, if txSckoInversion is false), ‘true’: SDO bit starts at rising edge which goes before the above mentioned falling edge, i.e.
the SDO signal is advanced by 0.5 SCK period (if txSckoInversion is false). If txSckoInversion is true - the rising/falling edges just swaps in above explanations. Effective only in slave mode, must be false in master mode.
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bool
txSckoInversion TX SCKO polarity: ‘false’: When transmitter is in master mode, serial data is transmitted off the falling bit clock edge (accordingly to the I2S Standard); ‘true’: When transmitter is in master mode, serial data is transmitted off the rising bit clock edge.
Effective only in master mode.
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bool
txSckiInversion TX SCKI polarity: ‘false’: When transmitter is in slave mode, serial data is transmitted off the falling bit clock edge (accordingly to the I2S Standard); ‘true’: When transmitter is in slave mode, serial data is transmitted off the rising bit clock edge.
Effective only in slave mode.
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uint8_t
txChannels Number of TX channels, valid range is 1…8 for TDM modes.
In the I2S and Left Justified modes the value of this parameter is ignored - the real number of channels is always 2 in these modes.
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cy_en_i2s_len_t
txChannelLength TX channel length, see cy_en_i2s_len_t, the value of this parameter is ignored in TDM modes, the real channel length is 32 bit in these modes.
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cy_en_i2s_len_t
txWordLength TX word length, see cy_en_i2s_len_t, must be less or equal to txChannelLength.
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cy_en_i2s_overhead_t
txOverheadValue TX overhead bits value when the word length is less than the channel length.
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uint8_t
txFifoTriggerLevel TX FIFO interrupt trigger level (0, 1, …, 255).
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bool
rxMasterMode ‘false’: RX in slave mode, ‘true’: RX in master mode.
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cy_en_i2s_alignment_t
rxAlignment RX data alignment, see: cy_en_i2s_alignment_t.
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cy_en_i2s_ws_pw_t
rxWsPulseWidth RX Word Select pulse width.
The value of this parameter is ignored in I2S and Left Justified modes the WS pulse width is always “one channel length” in these modes.
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bool
rxWatchdogEnable ‘false’: RX watchdog disabled, ‘true’: RX watchdog enabled.
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uint32_t
rxWatchdogValue RX watchdog counter value (32 bit).
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bool
rxSdiLatchingTime ‘false’: SDI bit starts at falling edge (accordingly to the I2S Standard if rxSckoInversion is false), ‘true’: SDI bit starts at rising edge that goes after the above mentioned falling edge, i.e.
the SDI signal is delayed by 0.5 SCK period (if rxSckoInversion is false). If rxSckoInversion is true - the rising/falling edges just swaps in above explanations. Effective only in master mode, must be false in slave mode.
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bool
rxSckoInversion RX SCKO polarity: ‘false’: When receiver is in master mode, serial data is captured by the rising bit clock edge (accordingly to the I2S Standard); ‘true’: When receiver is in master mode, serial data is captured by the falling bit clock edge.
Effective only in master mode.
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bool
rxSckiInversion RX SCKI polarity: ‘false’: When receiver is in slave mode, serial data is captured by the rising bit clock edge (accordingly to the I2S Standard); ‘true’: When receiver is in slave mode, serial data is captured by the falling bit clock edge.
Effective only in slave mode.
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uint8_t
rxChannels Number of RX channels, valid range is 1…8 for TDM modes.
In the I2S and Left Justified modes the value of this parameter is ignored - the real number of channels is always 2 in these modes.
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cy_en_i2s_len_t
rxChannelLength RX channel length, see cy_en_i2s_len_t, the value of this parameter is ignored in TDM modes, the real channel length is 32 bit in these modes.
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cy_en_i2s_len_t
rxWordLength RX word length, see cy_en_i2s_len_t, must be less or equal to rxChannelLength.
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bool
rxSignExtension RX value sign extension (when the word length is less than 32 bits), ‘false’: all MSB are filled by zeroes, ‘true’: all MSB are filled by the original sign bit value.
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uint8_t
rxFifoTriggerLevel RX FIFO interrupt trigger level (0, 1, …, (255 - (number of channels))).
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bool
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struct
cy_stc_i2s_context_t - #include <>
The I2S backup structure type to be used for the SysPm callback.
Cy_I2S_DeepSleepCallback context definition.
Public Members
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uint32_t
enableState Stores the I2S state.
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uint32_t
interruptMask Stores the I2S interrupt mask.
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uint32_t
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struct