cy_sysclk_8h

Provides an API declaration of the sysclk driver.

Version

3.20

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0
Copyright

Copyright 2016-2021 Cypress Semiconductor Corporation SPDX-License-Identifier: Apache-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Defines

CY_SYSCLK_DRV_VERSION_MAJOR

Driver major version.

CY_SYSCLK_DRV_VERSION_MINOR

Driver minor version.

CY_SYSCLK_ID

Sysclk driver identifier.

CY_SYSCLK_ILO_FREQ

ILO clock frequency.

CY_SYSCLK_WCO_FREQ

WCO clock frequency.

CY_SYSCLK_PILO_FREQ

PILO clock frequency.

CY_SYSCLK_IMO_FREQ

IMO clock frequency.

CY_SYSCLK_MFO_FREQ

MFO clock frequency.

CY_SYSCLK_PILO_TRIM_STEP

CY_SYSCLK_PILO_TRIM_STEP is the default PILO TRIM Step value.

CY_SYSCLK_ECOSTAT_AMPLITUDE

ECO does not have sufficient amplitude.

CY_SYSCLK_ECOSTAT_INACCURATE

ECO may not be meeting accuracy and duty cycle specs.

CY_SYSCLK_ECOSTAT_STABLE

ECO has fully stabilized.

Enums

enum cy_en_sysclk_status_t

cy_en_sysclk_status_t: Defines general-purpose function return values.

Values:

enumerator CY_SYSCLK_SUCCESS

Command completed with no errors.

enumerator CY_SYSCLK_BAD_PARAM

Invalid function input parameter.

enumerator CY_SYSCLK_TIMEOUT

Timeout occurred.

enumerator CY_SYSCLK_INVALID_STATE

Clock is in an invalid state.

enum cy_en_clkpath_in_sources_t

cy_en_clkpath_in_sources_t: Input multiplexer clock sources.

Values:

enumerator CY_SYSCLK_CLKPATH_IN_IMO

Select the IMO as the output of the path mux.

enumerator CY_SYSCLK_CLKPATH_IN_EXT

Select the EXT as the output of the path mux.

enumerator CY_SYSCLK_CLKPATH_IN_ECO

Select the ECO as the output of the path mux.

enumerator CY_SYSCLK_CLKPATH_IN_ALTHF

Select the ALTHF as the output of the path mux.

enumerator CY_SYSCLK_CLKPATH_IN_DSIMUX

Select the DSI MUX output as the output of the path mux.

enumerator CY_SYSCLK_CLKPATH_IN_LPECO

Select the LPECO as the output of the path mux.

enumerator CY_SYSCLK_CLKPATH_IN_IHO

Select the IHO as the output of the path mux.

enumerator CY_SYSCLK_CLKPATH_IN_DSI

Select a DSI signal (0 - 15) as the output of the DSI mux and path mux.

Make sure the DSI clock sources are available on used device.

enumerator CY_SYSCLK_CLKPATH_IN_ILO

Select the ILO (16) as the output of the DSI mux and path mux.

enumerator CY_SYSCLK_CLKPATH_IN_WCO

Select the WCO (17) as the output of the DSI mux and path mux.

enumerator CY_SYSCLK_CLKPATH_IN_ALTLF

Select the ALTLF (18) as the output of the DSI mux and path mux.

Make sure the ALTLF clock sources in available on used device.

enumerator CY_SYSCLK_CLKPATH_IN_PILO

Select the PILO (19) as the output of the DSI mux and path mux.

Make sure the PILO clock sources in available on used device.

enumerator CY_SYSCLK_CLKPATH_IN_ILO1

Select the ILO1(20) as the output of the path mux.

enum cy_en_fll_pll_output_mode_t

cy_en_fll_pll_output_mode_t: FLL and PLL output mode.

See registers CLK_FLL_CONFIG3 and CLK_PLL_CONFIG0, bits BYPASS_SEL.

Values:

enumerator CY_SYSCLK_FLLPLL_OUTPUT_AUTO

Output FLL/PLL input source when not locked, and FLL/PLL output when locked.

enumerator CY_SYSCLK_FLLPLL_OUTPUT_AUTO1

Same as AUTO.

enumerator CY_SYSCLK_FLLPLL_OUTPUT_INPUT

Output FLL/PLL input source regardless of lock status.

enumerator CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT

Output FLL/PLL output regardless of lock status.

This can be dangerous if used to clock clkHf, because FLL/PLL output may be unstable

enum cy_en_fll_cco_ranges_t

cy_en_fll_cco_ranges_t: FLL current-controlled oscillator (CCO) frequency ranges.

See register CLK_FLL_CONFIG4, bits CCO_RANGE.

Values:

enumerator CY_SYSCLK_FLL_CCO_RANGE0

Target frequency is in range 48 - 64 MHz.

enumerator CY_SYSCLK_FLL_CCO_RANGE1

Target frequency is in range 64 - 85 MHz.

enumerator CY_SYSCLK_FLL_CCO_RANGE2

Target frequency is in range 85 - 113 MHz.

enumerator CY_SYSCLK_FLL_CCO_RANGE3

Target frequency is in range 113 - 150 MHz.

enumerator CY_SYSCLK_FLL_CCO_RANGE4

Target frequency is in range 150 - 200 MHz.

enum cy_en_meas_clks_t

cy_en_meas_clks_t: Defines all possible clock sources.

Values:

enumerator CY_SYSCLK_MEAS_CLK_NC
enumerator CY_SYSCLK_MEAS_CLK_ILO
enumerator CY_SYSCLK_MEAS_CLK_WCO
enumerator CY_SYSCLK_MEAS_CLK_BAK
enumerator CY_SYSCLK_MEAS_CLK_ALTLF
enumerator CY_SYSCLK_MEAS_CLK_LFCLK
enumerator CY_SYSCLK_MEAS_CLK_IMO
enumerator CY_SYSCLK_MEAS_CLK_SLPCTRL
enumerator CY_SYSCLK_MEAS_CLK_PILO
enumerator CY_SYSCLK_MEAS_CLK_ILO1
enumerator CY_SYSCLK_MEAS_CLK_ECO_PRESCALER
enumerator CY_SYSCLK_MEAS_CLK_LPECO
enumerator CY_SYSCLK_MEAS_CLK_LPECO_PRESCALER
enumerator CY_SYSCLK_MEAS_CLK_MFO
enumerator CY_SYSCLK_MEAS_CLK_FAST_CLKS
enumerator CY_SYSCLK_MEAS_CLK_ECO
enumerator CY_SYSCLK_MEAS_CLK_EXT
enumerator CY_SYSCLK_MEAS_CLK_ALTHF
enumerator CY_SYSCLK_MEAS_CLK_TIMERCLK
enumerator CY_SYSCLK_MEAS_CLK_IHO
enumerator CY_SYSCLK_MEAS_CLK_PWR
enumerator CY_SYSCLK_MEAS_CLK_PATH_CLKS
enumerator CY_SYSCLK_MEAS_CLK_PATH0
enumerator CY_SYSCLK_MEAS_CLK_PATH1
enumerator CY_SYSCLK_MEAS_CLK_PATH2
enumerator CY_SYSCLK_MEAS_CLK_PATH3
enumerator CY_SYSCLK_MEAS_CLK_PATH4
enumerator CY_SYSCLK_MEAS_CLK_PATH5
enumerator CY_SYSCLK_MEAS_CLK_PATH6
enumerator CY_SYSCLK_MEAS_CLK_PATH7
enumerator CY_SYSCLK_MEAS_CLK_PATH8
enumerator CY_SYSCLK_MEAS_CLK_PATH9
enumerator CY_SYSCLK_MEAS_CLK_PATH10
enumerator CY_SYSCLK_MEAS_CLK_PATH11
enumerator CY_SYSCLK_MEAS_CLK_PATH12
enumerator CY_SYSCLK_MEAS_CLK_PATH13
enumerator CY_SYSCLK_MEAS_CLK_PATH14
enumerator CY_SYSCLK_MEAS_CLK_PATH15
enumerator CY_SYSCLK_MEAS_CLK_CLKHFS
enumerator CY_SYSCLK_MEAS_CLK_CLKHF0
enumerator CY_SYSCLK_MEAS_CLK_CLKHF1
enumerator CY_SYSCLK_MEAS_CLK_CLKHF2
enumerator CY_SYSCLK_MEAS_CLK_CLKHF3
enumerator CY_SYSCLK_MEAS_CLK_CLKHF4
enumerator CY_SYSCLK_MEAS_CLK_CLKHF5
enumerator CY_SYSCLK_MEAS_CLK_CLKHF6
enumerator CY_SYSCLK_MEAS_CLK_CLKHF7
enumerator CY_SYSCLK_MEAS_CLK_CLKHF8
enumerator CY_SYSCLK_MEAS_CLK_CLKHF9
enumerator CY_SYSCLK_MEAS_CLK_CLKHF10
enumerator CY_SYSCLK_MEAS_CLK_CLKHF11
enumerator CY_SYSCLK_MEAS_CLK_CLKHF12
enumerator CY_SYSCLK_MEAS_CLK_CLKHF13
enumerator CY_SYSCLK_MEAS_CLK_CLKHF14
enumerator CY_SYSCLK_MEAS_CLK_CLKHF15
enumerator CY_SYSCLK_MEAS_CLK_LAST_CLK
enum cy_en_wco_bypass_modes_t

cy_en_wco_bypass_modes_t: WCO bypass modes.

Values:

enumerator CY_SYSCLK_WCO_NOT_BYPASSED

WCO is not bypassed crystal is used.

enumerator CY_SYSCLK_WCO_BYPASSED

WCO is bypassed external clock must be supplied on XTAL pin.

enum cy_en_clkhf_in_sources_t

cy_en_clkhf_in_sources_t: Selects which clkHf input, or root mux, to configure.

See CLK_ROOT_SELECT registers, bits ROOT_MUX. Used with functions Cy_SysClk_ClkHfSetSource and Cy_SysClk_ClkHfGetSource.

Values:

enumerator CY_SYSCLK_CLKHF_IN_CLKPATH0

clkHf input is Clock Path 0

enumerator CY_SYSCLK_CLKHF_IN_CLKPATH1

clkHf input is Clock Path 1

enumerator CY_SYSCLK_CLKHF_IN_CLKPATH2

clkHf input is Clock Path 2

enumerator CY_SYSCLK_CLKHF_IN_CLKPATH3

clkHf input is Clock Path 3

enumerator CY_SYSCLK_CLKHF_IN_CLKPATH4

clkHf input is Clock Path 4

enumerator CY_SYSCLK_CLKHF_IN_CLKPATH5

clkHf input is Clock Path 5

enumerator CY_SYSCLK_CLKHF_IN_CLKPATH6

clkHf input is Clock Path 6

enumerator CY_SYSCLK_CLKHF_IN_CLKPATH7

clkHf input is Clock Path 7

enumerator CY_SYSCLK_CLKHF_IN_CLKPATH8

clkHf input is Clock Path 8

enumerator CY_SYSCLK_CLKHF_IN_CLKPATH9

clkHf input is Clock Path 9

enumerator CY_SYSCLK_CLKHF_IN_CLKPATH10

clkHf input is Clock Path 10

enumerator CY_SYSCLK_CLKHF_IN_CLKPATH11

clkHf input is Clock Path 11

enumerator CY_SYSCLK_CLKHF_IN_CLKPATH12

clkHf input is Clock Path 12

enumerator CY_SYSCLK_CLKHF_IN_CLKPATH13

clkHf input is Clock Path 13

enumerator CY_SYSCLK_CLKHF_IN_CLKPATH14

clkHf input is Clock Path 14

enumerator CY_SYSCLK_CLKHF_IN_CLKPATH15

clkHf input is Clock Path 15

enum cy_en_clkhf_dividers_t

cy_en_clkhf_dividers_t: clkHf divider values.

See CLK_ROOT_SELECT registers, bits ROOT_DIV. Used with functions Cy_SysClk_ClkHfSetDivider and Cy_SysClk_ClkHfGetDivider.

Values:

enumerator CY_SYSCLK_CLKHF_NO_DIVIDE

don’t divide clkHf

enumerator CY_SYSCLK_CLKHF_DIVIDE_BY_2

divide clkHf by 2

enumerator CY_SYSCLK_CLKHF_DIVIDE_BY_4

divide clkHf by 4

enumerator CY_SYSCLK_CLKHF_DIVIDE_BY_8

divide clkHf by 8

enum cy_en_divider_types_t

cy_en_divider_types_t: Programmable clock divider types.

Values:

enumerator CY_SYSCLK_DIV_8_BIT

Divider Type is an 8 bit divider.

enumerator CY_SYSCLK_DIV_16_BIT

Divider Type is a 16 bit divider.

enumerator CY_SYSCLK_DIV_16_5_BIT

Divider Type is a 16.5 bit fractional divider.

enumerator CY_SYSCLK_DIV_24_5_BIT

Divider Type is a 24.5 bit fractional divider.

enum cy_en_clklf_in_sources_t

cy_en_clklf_in_sources_t: Low frequency (clkLf) input sources.

See CLK_SELECT register, LFCLK_SEL bits. Used with functions Cy_SysClk_ClkLfSetSource, and Cy_SysClk_ClkLfGetSource.

Values:

enumerator CY_SYSCLK_CLKLF_IN_ILO

clkLf is sourced by the internal low speed oscillator (ILO)

enumerator CY_SYSCLK_CLKLF_IN_WCO

clkLf is sourced by the watch crystal oscillator (WCO)

enumerator CY_SYSCLK_CLKLF_IN_ALTLF

clkLf is sourced by the Alternate Low Frequency Clock (ALTLF)

enumerator CY_SYSCLK_CLKLF_IN_PILO

clkLf is sourced by the precision low speed oscillator (PILO)

enum cy_en_clktimer_in_sources_t

cy_en_clktimer_in_sources_t: Timer clock (clk_timer) input sources.

See CLK_TIMER_CTL register, TIMER_SEL and TIMER_HF0_DIV bits. Used with functions Cy_SysClk_ClkTimerSetSource, and Cy_SysClk_ClkTimerGetSource.

Values:

enumerator CY_SYSCLK_CLKTIMER_IN_IMO

clk_timer is sourced by the internal main oscillator (IMO)

enumerator CY_SYSCLK_CLKTIMER_IN_HF0_NODIV

clk_timer is sourced by clkHf[0] undivided

enumerator CY_SYSCLK_CLKTIMER_IN_HF0_DIV2

clk_timer is sourced by clkHf[0] divided by 2

enumerator CY_SYSCLK_CLKTIMER_IN_HF0_DIV4

clk_timer is sourced by clkHf[0] divided by 4

enumerator CY_SYSCLK_CLKTIMER_IN_HF0_DIV8

clk_timer is sourced by clkHf[0] divided by 8

enum cy_en_clkpump_in_sources_t

cy_en_clkpump_in_sources_t: Pump clock (clk_pump) input sources.

See CLK_SELECT register, PUMP_SEL bits. Used with functions Cy_SysClk_ClkPumpSetSource, and Cy_SysClk_ClkPumpGetSource.

note

This enum is available for CAT1A devices.

Values:

enumerator CY_SYSCLK_PUMP_IN_CLKPATH0

Pump clock input is clock path 0.

enumerator CY_SYSCLK_PUMP_IN_CLKPATH1

Pump clock input is clock path 1.

enumerator CY_SYSCLK_PUMP_IN_CLKPATH2

Pump clock input is clock path 2.

enumerator CY_SYSCLK_PUMP_IN_CLKPATH3

Pump clock input is clock path 3.

enumerator CY_SYSCLK_PUMP_IN_CLKPATH4

Pump clock input is clock path 4.

enumerator CY_SYSCLK_PUMP_IN_CLKPATH5

Pump clock input is clock path 5.

enumerator CY_SYSCLK_PUMP_IN_CLKPATH6

Pump clock input is clock path 6.

enumerator CY_SYSCLK_PUMP_IN_CLKPATH7

Pump clock input is clock path 7.

enumerator CY_SYSCLK_PUMP_IN_CLKPATH8

Pump clock input is clock path 8.

enumerator CY_SYSCLK_PUMP_IN_CLKPATH9

Pump clock input is clock path 9.

enumerator CY_SYSCLK_PUMP_IN_CLKPATH10

Pump clock input is clock path 10.

enumerator CY_SYSCLK_PUMP_IN_CLKPATH11

Pump clock input is clock path 11.

enumerator CY_SYSCLK_PUMP_IN_CLKPATH12

Pump clock input is clock path 12.

enumerator CY_SYSCLK_PUMP_IN_CLKPATH13

Pump clock input is clock path 13.

enumerator CY_SYSCLK_PUMP_IN_CLKPATH14

Pump clock input is clock path 14.

enumerator CY_SYSCLK_PUMP_IN_CLKPATH15

Pump clock input is clock path 15.

enum cy_en_clkpump_divide_t

cy_en_clkpump_divide_t: Pump clock (clk_pump) divide options.

See CLK_SELECT register, PUMP_DIV bits. Used with functions Cy_SysClk_ClkPumpSetDivider, and Cy_SysClk_ClkPumpGetDivider.

Values:

enumerator CY_SYSCLK_PUMP_NO_DIV

No division on pump clock.

enumerator CY_SYSCLK_PUMP_DIV_2

Pump clock divided by 2.

enumerator CY_SYSCLK_PUMP_DIV_4

Pump clock divided by 4.

enumerator CY_SYSCLK_PUMP_DIV_8

Pump clock divided by 8.

enumerator CY_SYSCLK_PUMP_DIV_16

Pump clock divided by 16.

enum cy_en_clkbak_in_sources_t

cy_en_clkbak_in_sources_t: Backup domain clock (clk_bak) input sources.

See BACKUP->CTL register, CLK_SEL bits. Used with functions Cy_SysClk_ClkBakSetSource, and Cy_SysClk_ClkBakGetSource.

note

THis enum is available for CAT1A devices.

Values:

enumerator CY_SYSCLK_BAK_IN_WCO

Backup domain clock input is WCO.

enumerator CY_SYSCLK_BAK_IN_CLKLF

Backup domain clock input is clkLf.

note

This parameter is available for CAT1A devices.

Functions

void Cy_SysClk_ExtClkSetFrequency(uint32_t freq)

Sets the signal frequency of the External Clock Source (EXTCLK) into the internal storage to be used in Cy_SysClk_ClkHfGetFrequency.

Function Usage

    /* Scenario: External precision 5MHz clock is needed to source clock path 1. */

    /* Configure the pin P0_5 to be an external clock input */
    (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 5, CY_GPIO_DM_HIGHZ, 0x00u, P0_5_SRSS_EXT_CLK);
    /* Set the EXTCLK frequency to 5MHz */
    Cy_SysClk_ExtClkSetFrequency(5000000UL);
    /* Set the EXTCLK as the source for clock path 1 */
    (void)Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_EXT);

    /* In case if there is a need to get the EXT CLK frequency */
    uint32_t extClkFreq = Cy_SysClk_ExtClkGetFrequency();

Parameters

freq – The frequency of the External Clock Source.

uint32_t Cy_SysClk_ExtClkGetFrequency(void)

Returns the frequency of the External Clock Source (EXTCLK) from the internal storage.

Function Usage

    /* Scenario: External precision 5MHz clock is needed to source clock path 1. */

    /* Configure the pin P0_5 to be an external clock input */
    (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 5, CY_GPIO_DM_HIGHZ, 0x00u, P0_5_SRSS_EXT_CLK);
    /* Set the EXTCLK frequency to 5MHz */
    Cy_SysClk_ExtClkSetFrequency(5000000UL);
    /* Set the EXTCLK as the source for clock path 1 */
    (void)Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_EXT);

    /* In case if there is a need to get the EXT CLK frequency */
    uint32_t extClkFreq = Cy_SysClk_ExtClkGetFrequency();

Returns

The frequency of the External Clock Source.

cy_en_sysclk_status_t Cy_SysClk_EcoConfigure(uint32_t freq, uint32_t cSum, uint32_t esr, uint32_t driveLevel)

Configures the external crystal oscillator (ECO) trim bits based on crystal characteristics.

This function should be called only when the ECO is disabled.

note

For CAT1B Devices: cSum stands for crystal load capacitance in pF.

note

Behavior of this API is IP dependent.
On CAT1A device:
For the PSoC 64 devices there are possible situations when function returns the PRA error status code. This is because for PSoC 64 devices the function uses the PRA driver to change the protected registers. Refer to cy_en_pra_status_t for more details. The following calculations are implemented in the 32-bit integer math: On PSoC 64 devices the configuration on the PRA driver will be reflected after Cy_SysClk_EcoEnable call.

*   freqKhz = freq / 1000
*   maxAmpl = sqrt(drivelevel / 2 / esr) / 3.14 / freqKhz / cSum
*   ampSect = INT(5 * 4 * 3.14^2 * freqKhz^2 * cSum^2 * 4 * esr / 1000000000 / 1000000 / 9)
*   As a result of the above calculations, max amplitude must be >= 0.65V, and the
*   number of amplifier sections must be <= 3, otherwise this function returns with
*   a parameter error.
*
*   atrim = 15
*   agc_en = 1
*   wdtrim = 7
*   gtrim = ampSect > 1 ? ampSect : ampSect == 1 ? 0 : 1
*   rtrim = 0
*   ftrim = 3
*

note

On CAT1B Device:
* No TRIM registers configuration required for CAT1B devices, For legacy API is emptied* The following calculations are implemented, generally in floating point:* freqMHz = freq / 1000000* max amplitude Vpp = 1000 * sqrt(drivelevel / 2 / esr) / 3.14 / freqMHz / cLoad* gm_min mA/V = 5 * 4 * 3.14 * 3.14 * freqMhz^2 * cLoad^2 * 4 * esr / 1000000000* Number of amplifier sections = INT(gm_min / 4.5)** As a result of the above calculations, max amplitude must be >= 0.5, and the* number of amplifier sections must be <= 3, otherwise this function returns with* a parameter error.** atrim = if (max amplitude < 0.5) then error* else 2 * the following:* max amplitude < 0.6: 0* max amplitude < 0.7: 1* max amplitude < 0.8: 2* max amplitude < 0.9: 3* max amplitude < 1.15: 5* max amplitude < 1.275: 6* max amplitude >= 1.275: 7* wdtrim = if (max amplitude < 0.5) then error* else 2 * the following:* max amplitude < 1.2: INT(5 * max amplitude) - 2* max amplitude >= 1.2: 3* gtrim = if (number of amplifier sections > 3) then error* else the following:* number of amplifier sections > 1: number of amplifier sections* number of amplifier sections = 1: 0* number of amplifier sections < 1: 1* rtrim = if (gtrim = error) then error* else the following:* freqMHz > 26.8: 0* freqMHz > 23.33: 1* freqMHz > 16.5: 2* freqMHz <= 16.5: 3* ftrim = if (atrim = error) then error* else INT(atrim / 2)*

Function Usage

    /* Scenario: ECO needs to be configured. The ECO pins are configured using
                 the gpio driver (SRSS_ECO_IN_PIN, SRSS_ECO_OUT_PIN). The ECO
                 crystal has the following characteristics:
                   Frequency: 17.2032 MHz
                   Parallel load crystal capacitance: 22 pF
                   Crystal shunt capacitance: 7 pF
                   Effective series resistance: 40 Ohm
                   Drive level: 500 uW */

    /* Disable the ECO before configuring */
    Cy_SysClk_EcoDisable();

    /* Configure the ECO with its characteristics */
    if(CY_SYSCLK_SUCCESS != Cy_SysClk_EcoConfigure(17203200UL,  /* 17.2032 MHz */
                                                   29UL,        /* 7 pF C0 + 22 pF Cload */
                                                   40UL,        /* 40 Ohms */
                                                   500UL))      /* 500 uW */
    {
        /* Insert error handling */
    }

    /* Enable the ECO with a timeout of 3000 microseconds */
    if(CY_SYSCLK_SUCCESS != Cy_SysClk_EcoEnable(3000UL))
    {
        /* Insert error handling */
    }

Parameters
  • freq – Operating frequency of the crystal in Hz. Valid range: 16000000…35000000 (16..35 MHz).

  • cSum – The summary capacitance of C0 (the crystal itself shunt capacitance) and Cload (the parallel load capacitance), in pF. So cSum = C0 + Cload. Valid range: 1…100.

  • esr – Effective series resistance of the crystal in Ohms. Valid range: 1…1000.

  • driveLevel – Crystal drive level in uW. Valid range: 1…2000.

Returns

Error / status code:

CY_SYSCLK_SUCCESS - ECO configuration completed successfully

CY_SYSCLK_BAD_PARAM - One or more invalid parameters

CY_SYSCLK_INVALID_STATE - ECO already enabled

cy_en_sysclk_status_t Cy_SysClk_EcoEnable(uint32_t timeoutus)

Enables the external crystal oscillator (ECO).

This function should be called after Cy_SysClk_EcoConfigure.

note

Call SystemCoreClockUpdate after this function calling if it affects the CLK_HF0 frequency.

Function Usage

    /* Scenario: ECO is successfully configured and needs to be enabled. The
                 ECO pins are configured using the gpio driver
                 (SRSS_ECO_IN_PIN, SRSS_ECO_OUT_PIN). */

    uint32_t ecofreq = 0UL; /* Variable to store the ECO frequency */

    /* Enable the ECO with a timeout of 1000 microseconds */
    if(CY_SYSCLK_SUCCESS == Cy_SysClk_EcoEnable(1000UL))
    {
        ecofreq = Cy_SysClk_EcoGetFrequency();
        /* Now ecofreq contains an actual ECO frequency */
    }
    else
    {
        /* Insert error handling */
    }

    /* Set the path muxes and configure the downstream clocks. For example,
       the ECO can source the FLL through path 0 clock or it can source the PLL
       through path 1 clock. */

Parameters

timeoutus – Amount of time in microseconds to wait for the ECO to stabilize. To avoid waiting for stabilization, set this parameter to 0.

Returns

Error / status code:

CY_SYSCLK_SUCCESS - ECO locked

CY_SYSCLK_TIMEOUT - ECO timed out and did not lock

CY_SYSCLK_INVALID_STATE - ECO already enabled For the PSoC 64 devices there are possible situations when function returns the PRA error status code. This is because for PSoC 64 devices the function uses the PRA driver to change the protected registers. Refer to

cy_en_pra_status_t for more details.

uint32_t Cy_SysClk_EcoGetFrequency(void)

Returns the frequency of the external crystal oscillator (ECO).

note

If the ECO is not enabled or stable - a zero is returned.

note

This API is available for CAT1A devices.

Function Usage

    /* Scenario: ECO is successfully configured and needs to be enabled. The
                 ECO pins are configured using the gpio driver
                 (SRSS_ECO_IN_PIN, SRSS_ECO_OUT_PIN). */

    uint32_t ecofreq = 0UL; /* Variable to store the ECO frequency */

    /* Enable the ECO with a timeout of 1000 microseconds */
    if(CY_SYSCLK_SUCCESS == Cy_SysClk_EcoEnable(1000UL))
    {
        ecofreq = Cy_SysClk_EcoGetFrequency();
        /* Now ecofreq contains an actual ECO frequency */
    }
    else
    {
        /* Insert error handling */
    }

    /* Set the path muxes and configure the downstream clocks. For example,
       the ECO can source the FLL through path 0 clock or it can source the PLL
       through path 1 clock. */

Returns

The frequency of the ECO.

void Cy_SysClk_EcoDisable(void)

Disables the external crystal oscillator (ECO).

This function should not be called if the ECO is sourcing clkHf[0].

Function Usage

    /* Scenario: ECO sources path 2 clock, which sources HFCLK2. The ECO needs
                 to be disabled and replaced with the IMO for HFCLK2 */

    /* Update the path 2 clock to IMO */
    (void)Cy_SysClk_ClkPathSetSource(2UL, CY_SYSCLK_CLKPATH_IN_IMO);

    /* Disable the ECO */
    Cy_SysClk_EcoDisable();

uint32_t Cy_SysClk_EcoGetStatus(void)

Reports the current status of the external crystal oscillator (ECO).

Function Usage

    /* Scenario: Query the status of the ECO */

    uint32_t ecoStatus = Cy_SysClk_EcoGetStatus();

    /* Perform action based on the ECO status */
    switch(ecoStatus)
    {
        case CY_SYSCLK_ECOSTAT_AMPLITUDE:
            /* Amplitude is not sufficient. Try waiting longer before
               attempting to reconfigure the ECO */
        break;
        case CY_SYSCLK_ECOSTAT_INACCURATE:
            /* Amplitude is correct but the ECO is not yet stable. Try
               waiting longer before attempting to reconfigure the ECO */
        break;
        case CY_SYSCLK_ECOSTAT_STABLE:
            /* ECO is stable and ready for use */
        break;
        default:
            /* Invalid state. Perform error handling. */
        break;
    }

Returns

CY_SYSCLK_ECOSTAT_AMPLITUDE = ECO does not have sufficient amplitude

CY_SYSCLK_ECOSTAT_INACCURATE = ECO has sufficient amplitude but may not be meeting accuracy and duty cycle specifications

CY_SYSCLK_ECOSTAT_STABLE = ECO has fully stabilized

cy_en_sysclk_status_t Cy_SysClk_ClkPathSetSource(uint32_t clkPath, cy_en_clkpath_in_sources_t source)

Configures the source for the specified clock path.

note

If calling this function changes an FLL or PLL input frequency, disable the FLL or PLL before calling this function. After calling this function, call the FLL or PLL configure function, for example Cy_SysClk_FllConfigure().

note

Call SystemCoreClockUpdate after this function calling if it affects the CLK_HF0 frequency.

note

Call Cy_SysLib_SetWaitStates before calling this function if it affects the CLK_HF0 frequency and the frequency is increasing.

note

Call Cy_SysLib_SetWaitStates after calling this function if it affects the CLK_HF0 frequency and the frequency is decreasing.

Function Usage

    /* Scenario: ECO needs to source HFCLK2 through Path 2. The ECO is
                 configured through its function calls. */

    #define CLKPATH2 (2UL)
    #define HFCLK2 (2UL)

    uint32_t clkPathMuxFreq = 0UL; /* Variable to store the Clock Path Mux output frequency */

    /* Set the clock path 2 mux to be sourced from ECO */
    if(CY_SYSCLK_SUCCESS == Cy_SysClk_ClkPathSetSource(CLKPATH2, CY_SYSCLK_CLKPATH_IN_ECO))
    {
        clkPathMuxFreq = Cy_SysClk_ClkPathMuxGetFrequency(CLKPATH2);
        /* Now clkPathMuxFreq contains the Clock Path Mux output frequency */
    }
    else
    {
        /* Perform error handling */
    }

    /* Set the HFCLK2 source to clock path 2 and enable HFCLK2 */
    (void)Cy_SysClk_ClkHfSetSource(HFCLK2, CY_SYSCLK_CLKHF_IN_CLKPATH2);

    /* Enable HFCLK2  */
    (void)Cy_SysClk_ClkHfEnable(HFCLK2);

Parameters
  • clkPath – Selects which clock path to configure; 0 is the first clock path, which is the FLL.

  • sourcecy_en_clkpath_in_sources_t

Returns

cy_en_sysclk_status_t CY_SYSCLK_INVALID_STATE - ECO already enabled For the PSoC 64 devices there are possible situations when function returns the PRA error status code. This is because for PSoC 64 devices the function uses the PRA driver to change the protected registers. Refer to cy_en_pra_status_t for more details.

cy_en_clkpath_in_sources_t Cy_SysClk_ClkPathGetSource(uint32_t clkPath)

Reports which source is selected for the path mux.

Function Usage

    /* Scenario: A peripheral derived off of Path 1 clock is not clocking at the
                 expected frequency and accuracy. Need to confirm that the source
                 of the Path 1 mux is the ECO. */

    /* Get the source of the clock path 1 mux  */
    if(CY_SYSCLK_CLKPATH_IN_ECO != Cy_SysClk_ClkPathGetSource(1UL))
    {
        /* Insert error handling */
    }

Parameters

clkPath – Selects which clock path to report; 0 is the first clock path, which is the FLL.

Returns

cy_en_clkpath_in_sources_t

uint32_t Cy_SysClk_ClkPathMuxGetFrequency(uint32_t clkPath)

Returns the output frequency of the clock path mux.

note

If the return value equals zero, that means either:

  • the selected path mux source signal frequency is unknown (e.g. dsi_out, etc.) or

  • the selected path mux source is not configured/enabled/stable (e.g. ECO, EXTCLK, etc.).

Function Usage

    /* Scenario: ECO needs to source HFCLK2 through Path 2. The ECO is
                 configured through its function calls. */

    #define CLKPATH2 (2UL)
    #define HFCLK2 (2UL)

    uint32_t clkPathMuxFreq = 0UL; /* Variable to store the Clock Path Mux output frequency */

    /* Set the clock path 2 mux to be sourced from ECO */
    if(CY_SYSCLK_SUCCESS == Cy_SysClk_ClkPathSetSource(CLKPATH2, CY_SYSCLK_CLKPATH_IN_ECO))
    {
        clkPathMuxFreq = Cy_SysClk_ClkPathMuxGetFrequency(CLKPATH2);
        /* Now clkPathMuxFreq contains the Clock Path Mux output frequency */
    }
    else
    {
        /* Perform error handling */
    }

    /* Set the HFCLK2 source to clock path 2 and enable HFCLK2 */
    (void)Cy_SysClk_ClkHfSetSource(HFCLK2, CY_SYSCLK_CLKHF_IN_CLKPATH2);

    /* Enable HFCLK2  */
    (void)Cy_SysClk_ClkHfEnable(HFCLK2);

Returns

The output frequency of the path mux.

uint32_t Cy_SysClk_ClkPathGetFrequency(uint32_t clkPath)

Returns the output frequency of the clock path mux.

note

If the return value equals zero, that means either:

  • the selected path mux source signal frequency is unknown (e.g. dsi_out, etc.) or

  • the selected path mux source is not configured/enabled/stable (e.g. ECO, EXTCLK, etc.).

Function Usage

    /* Scenario: FLL is configured and needs to be enabled within 2 ms */

    #define CLKPATH0 (0UL)

    uint32_t clkPathFreq = 0UL; /* Variable to store the Clock Path output frequency */

    /* Enable the FLL with a timeout of 2000 microseconds */
    if (CY_SYSCLK_SUCCESS == Cy_SysClk_FllEnable(2000UL))
    {
        clkPathFreq = Cy_SysClk_ClkPathGetFrequency(CLKPATH0);
        /* Now clkPathFreq contains an actual FLL frequency */
    }
    else
    {
        /* Insert error handling */
    }

Returns

The output frequency of the path mux.

cy_en_sysclk_status_t Cy_SysClk_FllConfigure(uint32_t inputFreq, uint32_t outputFreq, cy_en_fll_pll_output_mode_t outputMode)

Configures the FLL, for best accuracy optimization.

note

Call this function after changing the FLL input frequency, for example if Cy_SysClk_ClkPathSetSource() is called.

note

Do not call this function when the FLL is enabled. If it is called, then this function returns with an CY_SYSCLK_INVALID_STATE return value and no register updates.

note

Call SystemCoreClockUpdate after this function calling if it affects the CLK_HF0 frequency.

note

Call Cy_SysLib_SetWaitStates before calling this function if the FLL is the source of CLK_HF0 and the FLL frequency is increasing.

note

Call Cy_SysLib_SetWaitStates after calling this function if the FLL is the source of CLK_HF0 and the FLL frequency is decreasing.

note

On PSoC 64 devices the configuration on the PRA driver will be reflected after Cy_SysClk_FllEnable call. Any call to Cy_SysClk_FllGetConfiguration before calling Cy_SysClk_FllEnable returns old configuration values.

Function Usage

    /* Scenario: FLL needs to source HFCLK0, which must operate at 100 MHz.
                 The IMO sources the FLL at 8MHz. Startup time is not an issue
                 and manual configuration of the FLL is not needed. */

    /* Set the FLL source (path 0 mux) to be the IMO */
    (void)Cy_SysClk_ClkPathSetSource(0UL, CY_SYSCLK_CLKPATH_IN_IMO);

    /* Auto-configure the FLL */
    if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllConfigure(CY_SYSCLK_IMO_FREQ,               /* Input clock = 8 MHz */
                                                    100000000UL,                      /* Output clock = 100 MHz */
                                                    CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT))  /* Bypass Mux to FLL Output */
    {
        /* Insert error handling */
    }

    /* Enable the FLL with 2000 microsecond timeout */
    if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllEnable(2000UL))
    {
        /* Insert error handling */
    }

    /* Set the HFCLK0 source to clock path 0 */
    (void)Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0);

Parameters
  • inputFreq – frequency of input source, in Hz

  • outputFreq – Desired FLL output frequency, in Hz. Allowable range is 24 MHz to 100 MHz. In all cases, FLL_OUTPUT_DIV must be set; the output divide by 2 option is required.

  • outputModecy_en_fll_pll_output_mode_t If output mode is bypass, then the output frequency equals the input source frequency regardless of the frequency parameter values.

Returns

Error / status code:

CY_SYSCLK_SUCCESS - FLL successfully configured

CY_SYSCLK_INVALID_STATE - FLL not configured because it is enabled

CY_SYSCLK_BAD_PARAM - desired output frequency is out of valid range

cy_en_sysclk_status_t Cy_SysClk_FllManualConfigure(const cy_stc_fll_manual_config_t *config)

Manually configures the FLL based on user inputs.

note

Call this function after changing the FLL input frequency, for example if Cy_SysClk_ClkPathSetSource() is called.

note

Do not call this function when the FLL is enabled. If it is called, then this function returns immediately with an CY_SYSCLK_INVALID_STATE return value and no register updates.

note

Call SystemCoreClockUpdate after this function calling if it affects the CLK_HF0 frequency.

note

Call Cy_SysLib_SetWaitStates before calling this function if the FLL is the source of CLK_HF0 and the FLL frequency is increasing.

note

Call Cy_SysLib_SetWaitStates after calling this function if the FLL is the source of CLK_HF0 and the FLL frequency is decreasing.

note

On PSoC 64 devices the configuration on the PRA driver will be reflected after Cy_SysClk_FllEnable call. Any call to Cy_SysClk_FllGetConfiguration before calling Cy_SysClk_FllEnable returns old configuration values.

Function Usage

    /* Scenario: FLL needs to source HFCLK0, which must operate at 100 MHz.
                 The IMO sources the FLL at 8MHz. The characteristics of the
                 FLL lock parameters are already known and the startup time
                 for the FLL configuration must be minimized. */

    /* Refer to the TRM for the full set of equations used to calculate the parameters */
    const cy_stc_fll_manual_config_t fllConfig =
    {
        /*.fllMult =*/         1725UL,                        /* Multiplier for CCO frequency */
        /*.refDiv =*/          (uint16_t)69u,                 /* Reference clock divider */
        /*.ccoRange =*/        CY_SYSCLK_FLL_CCO_RANGE4,      /* Target CCO range of 200 (100*2) MHz */
        /*.enableOutputDiv =*/ true,                          /* Output divider enabled (divide by 2) */
        /*.lockTolerance =*/   33u,                           /* Lock tolerance */
        /*.igain =*/           7u,                            /* FLL loop filter integral gain */
        /*.pgain =*/           5u,                            /* FLL loop filter proportional gain */
        /*.settlingCount =*/   8u,                            /* Wait count before loop measurement restarts */
        /*.outputMode =*/      CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT,/* Bypass Mux to FLL Output */
        /*.cco_Freq =*/        355u                           /* CCO frequency code (HW controlled during lock) */
    };

    /* Set the FLL source (path 0 mux) to be the IMO */
    (void)Cy_SysClk_ClkPathSetSource(0UL, CY_SYSCLK_CLKPATH_IN_IMO);

    /* Configure the FLL lock using pre-calculated values */
    if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllManualConfigure(&fllConfig))
    {
        /* Insert error handling */
    }

    /* Enable the FLL with 2000 microsecond timeout */
    if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllEnable(2000UL))
    {
        /* Insert error handling */
    }

    /* Set the HFCLK0 source to clock path 0 */
    (void)Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0);

Parameters

configcy_stc_fll_manual_config_t

Returns

Error / status code:

CY_SYSCLK_SUCCESS - FLL successfully configured

CY_SYSCLK_INVALID_STATE - FLL not configured because it is enabled CY_SYSCLK_INVALID_STATE - ECO already enabled For the PSoC 64 devices there are possible situations when function returns the PRA error status code. This is because for PSoC 64 devices the function uses the PRA driver to change the protected registers. Refer to cy_en_pra_status_t for more details.

void Cy_SysClk_FllGetConfiguration(cy_stc_fll_manual_config_t *config)

Reports the FLL configuration settings.

note

On PSoC 64 devices the configuration on the PRA driver will be reflected after Cy_SysClk_FllEnable call. Any call to Cy_SysClk_FllGetConfiguration before calling Cy_SysClk_FllEnable returns old configuration values.

Function Usage

    /* Scenario: The calculated FLL parameters need to be checked. */

    cy_stc_fll_manual_config_t fllConfig;

    /* Auto-configure the FLL */
    if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllConfigure(8000000UL,                        /* Input clock = 8 MHz */
                                                    100000000UL,                      /* Output clock = 100 MHz */
                                                    CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT))  /* Bypass Mux to FLL Output */
    {
        /* Insert error handling */
    }

    /* Retrieve the calculated parameters */
    Cy_SysClk_FllGetConfiguration(&fllConfig);

Parameters

configcy_stc_fll_manual_config_t

cy_en_sysclk_status_t Cy_SysClk_FllEnable(uint32_t timeoutus)

Enables the FLL.

The FLL should be configured before calling this function.

note

While waiting for the FLL to lock, the FLL bypass mode is set to CY_SYSCLK_FLLPLL_OUTPUT_INPUT. After the FLL is locked, the FLL bypass mdoe is then set to CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT.

note

Call SystemCoreClockUpdate after calling this function if it affects the CLK_HF0 frequency.

note

Call Cy_SysLib_SetWaitStates before calling this function if the FLL is the source of CLK_HF0 and the CLK_HF0 frequency is increasing.

Function Usage

    /* Scenario: FLL is configured and needs to be enabled within 2 ms */

    #define CLKPATH0 (0UL)

    uint32_t clkPathFreq = 0UL; /* Variable to store the Clock Path output frequency */

    /* Enable the FLL with a timeout of 2000 microseconds */
    if (CY_SYSCLK_SUCCESS == Cy_SysClk_FllEnable(2000UL))
    {
        clkPathFreq = Cy_SysClk_ClkPathGetFrequency(CLKPATH0);
        /* Now clkPathFreq contains an actual FLL frequency */
    }
    else
    {
        /* Insert error handling */
    }

Parameters

timeoutus – Amount of time in micro seconds to wait for FLL to lock. If lock doesn’t occur, the FLL is stopped. To avoid waiting for lock, set this to 0 and manually check for lock using Cy_SysClk_FllLocked.

Returns

Error / status code:

CY_SYSCLK_SUCCESS - FLL successfully enabled

CY_SYSCLK_TIMEOUT - Timeout waiting for FLL lock CY_SYSCLK_INVALID_STATE - ECO already enabled For the PSoC 64 devices there are possible situations when function returns the PRA error status code. This is because for PSoC 64 devices the function uses the PRA driver to change the protected registers. Refer to cy_en_pra_status_t for more details.

bool Cy_SysClk_FllIsEnabled(void)

Reports whether or not the FLL is enabled.

Function Usage

    /* Scenario: FLL failed to enable and must be reconfigured. Or the FLL is no
                 longer used and hence needs to be disabled. */

    if (Cy_SysClk_FllIsEnabled())
    {
        if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllDisable())
        {
            /* Insert error handling */
        }
    }

    /* The clocks that relied on the FLL will now run off of the clock that
       was used to source the FLL (e.g. IMO or ECO). */

Returns

false = disabled

true = enabled

bool Cy_SysClk_FllLocked(void)

Reports whether the FLL is locked first time during FLL starting.

Intended to be used with Cy_SysClk_FllEnable with zero timeout.

note

The unlock occurrence may appear during FLL normal operation, so this function is not recommended to check the FLL normal operation stability.

Function Usage

    /* Scenario: FLL is configured and needs to be enabled in a non-blocking way */

    /* Enable the FLL without timeout */
    (void)Cy_SysClk_FllEnable(0UL);

    /* Check the status of the lock */
    while(!Cy_SysClk_FllLocked())
    {
        /* Perform other actions while the FLL is locking */
    }

    /* FLL Locked. Proceed with further configuration */

Returns

false = not locked

true = locked

cy_en_sysclk_status_t Cy_SysClk_FllDisable(void)

Disables the FLL and the CCO.

note

Call SystemCoreClockUpdate after this function calling if it affects the CLK_HF0 frequency.

note

Call Cy_SysLib_SetWaitStates after calling this function if the FLL is the source of CLK_HF0 and the CLK_HF0 frequency is decreasing.

Function Usage

    /* Scenario: FLL failed to enable and must be reconfigured. Or the FLL is no
                 longer used and hence needs to be disabled. */

    if (Cy_SysClk_FllIsEnabled())
    {
        if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllDisable())
        {
            /* Insert error handling */
        }
    }

    /* The clocks that relied on the FLL will now run off of the clock that
       was used to source the FLL (e.g. IMO or ECO). */

Returns

cy_en_sysclk_status_t CY_SYSCLK_INVALID_STATE - ECO already enabled For the PSoC 64 devices there are possible situations when function returns the PRA error status code. This is because for PSoC 64 devices the function uses the PRA driver to change the protected registers. Refer to cy_en_pra_status_t for more details.

uint32_t Cy_SysClk_FllGetFrequency(void)

Returns the output frequency of the FLL.

note

If the return value equals zero, that means FLL is disabled.

Function Usage

    uint32_t freq = Cy_SysClk_FllGetFrequency();
    (void) freq; /* Supress 'unused variable' warning */

Returns

The output frequency of FLL.

cy_en_sysclk_status_t Cy_SysClk_PllConfigure(uint32_t clkPath, const cy_stc_pll_config_t *config)

Configures a given PLL.

The configuration formula used is: Fout = pll_clk * (P / Q / div_out), where: Fout is the desired output frequency pll_clk is the frequency of the input source P is the feedback divider. Its value is in bitfield FEEDBACK_DIV. Q is the reference divider. Its value is in bitfield REFERENCE_DIV. div_out is the reference divider. Its value is in bitfield OUTPUT_DIV.

note

Call this function after changing the PLL input frequency, for example if Cy_SysClk_ClkPathSetSource() is called.

note

Do not call this function when the PLL is enabled. If it is called, then this function returns immediately with an error return value and no register updates.

note

Call SystemCoreClockUpdate after this function calling if it affects the CLK_HF0 frequency.

note

Call Cy_SysLib_SetWaitStates before calling this function if the PLL is the source of CLK_HF0 and the PLL frequency is increasing.

note

Call Cy_SysLib_SetWaitStates after calling this function if the PLL is the source of CLK_HF0 and the PLL frequency is decreasing.

note

On PSoC 64 devices the configuration on the PRA driver will be reflected after Cy_SysClk_PllEnable call. Any call to Cy_SysClk_PllGetConfiguration before calling Cy_SysClk_PllEnable returns old configuration values.

Function Usage

    /* Scenario: PLL needs to source HFCLK0, which must operate at 100 MHz.
                 The IMO sources the PLL at 8MHz. Startup time is not an issue
                 and manual configuration of the PLL is not needed. */

    cy_stc_pll_config_t pllConfig =
    {
        /*.inputFreq  =*/ 8000000UL,                    /* PLL input: 8 MHz IMO */
        /*.outputFreq =*/ 100000000UL,                  /* PLL output: 100 MHz */
        /*.lfMode     =*/ true,                         /* Enable low frequency mode (VCO = 170~200 MHz) */
        /*.outputMode =*/ CY_SYSCLK_FLLPLL_OUTPUT_AUTO  /* Output 100 MHz when locked. Otherwise 8 MHz */
    };

    /* Set the PLL source (path 1 mux) to be the IMO.
       Note: Path 0 is not valid for PLL. */
    (void)Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO);

    /* Configure Path 1 PLL with the settings in pllConfig struct */
    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllConfigure(1UL, &pllConfig))
    {
        /* Insert error handling */
    }

    /* Enable the Path 1 PLL with 2000 microsecond timeout */
    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1UL, 2000UL))
    {
        /* Insert error handling */
    }

    /* Set the HFCLK0 source to clock path 1 */
    (void)Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1);

Parameters
  • clkPath – Selects which PLL to configure. 1 is the first PLL; 0 is invalid.

  • configcy_stc_pll_config_t

Returns

Error / status code:

CY_SYSCLK_SUCCESS - PLL successfully configured

CY_SYSCLK_INVALID_STATE - PLL not configured because it is enabled

CY_SYSCLK_BAD_PARAM - Invalid clock path number, or input or desired output frequency is out of valid range

cy_en_sysclk_status_t Cy_SysClk_PllManualConfigure(uint32_t clkPath, const cy_stc_pll_manual_config_t *config)

Manually configures a PLL based on user inputs.

note

Call this function after changing the PLL input frequency; for example if Cy_SysClk_ClkPathSetSource() is called.

note

Do not call this function when the PLL is enabled. If it is called, then this function returns immediately with an error return value and no register updates.

note

Call SystemCoreClockUpdate after this function calling if it affects the CLK_HF0 frequency.

note

Call Cy_SysLib_SetWaitStates before calling this function if the PLL is the source of CLK_HF0 and the PLL frequency is increasing.

note

Call Cy_SysLib_SetWaitStates after calling this function if the PLL is the source of CLK_HF0 and the PLL frequency is decreasing.

note

On PSoC 64 devices the configuration on the PRA driver will be reflected after Cy_SysClk_PllEnable call. Any call to Cy_SysClk_PllGetConfiguration before calling Cy_SysClk_PllEnable returns old configuration values.

Function Usage

    /* Scenario: PLL needs to source HFCLK0, which must operate at 100 MHz.
                 The IMO sources the PLL at 8MHz. The characteristics of the
                 PLL lock parameters are already known and the startup time
                 for the PLL configuration must be minimized. */

    /* Refer to the TRM for the full set of equations used to calculate the parameters */
    cy_stc_pll_manual_config_t pllConfig =
    {
        /*.feedbackDiv  =*/ 25u,                            /* Feedback divider */
        /*.referenceDiv =*/ 1u,                             /* Reference divider */
        /*.outputDiv    =*/ 2u,                             /* Output divider */
        /*.lfMode       =*/ true,                           /* Enable low frequency mode (VCO = 170~200 MHz) */
        /*.outputMode   =*/ CY_SYSCLK_FLLPLL_OUTPUT_AUTO    /* Output 100 MHz when locked. Otherwise 8 MHz */
    };

    /* Set the PLL source (path 1 mux) to be the IMO.
       Note: Path 0 is not valid for PLL. */
    (void)Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO);

    /* Configure Path 1 PLL with the settings in pllConfig struct */
    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(1UL, &pllConfig))
    {
        /* Insert error handling */
    }

    /* Enable the path 1 PLL with 2000 microsecond timeout */
    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1UL, 2000UL))
    {
        /* Insert error handling */
    }

    /* Set the HFCLK0 source to clock path 1 */
    (void)Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1);

Parameters
Returns

Error / status code:

CY_SYSCLK_SUCCESS - PLL successfully configured

CY_SYSCLK_INVALID_STATE - PLL not configured because it is enabled

CY_SYSCLK_BAD_PARAM - invalid clock path number CY_SYSCLK_INVALID_STATE - ECO already enabled For the PSoC 64 devices there are possible situations when function returns the PRA error status code. This is because for PSoC 64 devices the function uses the PRA driver to change the protected registers. Refer to

cy_en_pra_status_t for more details.

cy_en_sysclk_status_t Cy_SysClk_PllGetConfiguration(uint32_t clkPath, cy_stc_pll_manual_config_t *config)

Reports configuration settings for a PLL.

note

On PSoC 64 devices the configuration on the PRA driver will be reflected after Cy_SysClk_PllEnable call. Any call to Cy_SysClk_PllGetConfiguration before calling Cy_SysClk_PllEnable returns old configuration values.

Function Usage

    /* Scenario: The calculated PLL parameters need to be checked. */

    cy_stc_pll_config_t autoPllConfig =
    {
        /*.inputFreq  =*/ 8000000UL,                    /* PLL input: 8 MHz IMO */
        /*.outputFreq =*/ 100000000UL,                  /* PLL output: 100 MHz */
        /*.lfMode     =*/ true,                         /* Enable low frequency mode (VCO = 170~200 MHz) */
        /*.outputMode =*/ CY_SYSCLK_FLLPLL_OUTPUT_AUTO  /* Output 100 MHz when locked. Otherwise 8 MHz */
    };

    cy_stc_pll_manual_config_t getPllParams;

    /* Configure Path 1 PLL with the settings in pllConfig struct */
    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllConfigure(1UL, &autoPllConfig))
    {
        /* Insert error handling */
    }

    /* Retrieve the calculated parameters of Path 1 PLL */
    (void)Cy_SysClk_PllGetConfiguration(1UL, &getPllParams);

Parameters
Returns

Error / status code:

CY_SYSCLK_SUCCESS - PLL data successfully reported

CY_SYSCLK_BAD_PARAM - invalid clock path number CY_SYSCLK_INVALID_STATE - ECO already enabled For the PSoC 64 devices there are possible situations when function returns the PRA error status code. This is because for PSoC 64 devices the function uses the PRA driver to change the protected registers. Refer to cy_en_pra_status_t for more details.

cy_en_sysclk_status_t Cy_SysClk_PllEnable(uint32_t clkPath, uint32_t timeoutus)

Enables the PLL.

The PLL should be configured before calling this function.

note

Call SystemCoreClockUpdate after this function calling if it affects the CLK_HF0 frequency.

note

Call Cy_SysLib_SetWaitStates before calling this function if the PLL is the source of CLK_HF0 and the CLK_HF0 frequency is increasing.

note

Call Cy_SysLib_SetWaitStates after calling this function if the PLL is the source of CLK_HF0 and the CLK_HF0 frequency is decreasing.

Function Usage

    /* Scenario: PLL is configured and needs to be enabled within 2 ms */

    /* Enable the Path 1 PLL with a timeout of 2000 microsecond */
    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1UL, 2000UL))
    {
        /* Insert error handling */
    }

Parameters
  • clkPath – Selects which PLL to enable. 1 is the first PLL; 0 is invalid.

  • timeoutus – amount of time in microseconds to wait for the PLL to lock. If the lock doesn’t occur, PLL is stopped. To avoid waiting for lock, set this to 0 and manually check for lock using Cy_SysClk_PllLocked.

Returns

Error / status code:

CY_SYSCLK_SUCCESS - PLL successfully enabled

CY_SYSCLK_TIMEOUT - Timeout waiting for PLL lock

CY_SYSCLK_BAD_PARAM - invalid clock path number CY_SYSCLK_INVALID_STATE - ECO already enabled For the PSoC 64 devices there are possible situations when function returns the PRA error status code. This is because for PSoC 64 devices the function uses the PRA driver to change the protected registers. Refer to

cy_en_pra_status_t for more details.

bool Cy_SysClk_PllIsEnabled(uint32_t clkPath)

Reports whether or not the selected PLL is enabled.

Function Usage

    /* Scenario: Path 1 PLL failed to enable and must be reconfigured. Or the
                 PLL is no longer used and hence needs to be disabled. */

    if (Cy_SysClk_PllIsEnabled(1UL))
    {
        if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllDisable(1UL))
        {
            /* Insert error handling */
        }
    }

    /* The clocks that relied on the PLL will now run off of the clock that
       was used to source the FLL (e.g. IMO or ECO). */

Parameters

clkPath – Selects which PLL to check. 1 is the first PLL; 0 is invalid.

Returns

false = disabled

true = enabled

bool Cy_SysClk_PllLocked(uint32_t clkPath)

Reports whether or not the selected PLL is locked.

Function Usage

    /* Scenario: PLL is configured and needs to be enabled in a non-blocking way */

    /* Enable the Path 1 PLL without timeout */
    (void)Cy_SysClk_PllEnable(1UL, 0UL);

    /* Check the status of the lock */
    while(Cy_SysClk_PllLocked(1UL))
    {
        /* Perform other actions while the PLL is locking */
    }

    /* PLL Locked. Proceed with further configuration */

Parameters

clkPath – Selects which PLL to check. 1 is the first PLL; 0 is invalid.

Returns

false = not locked

true = locked

bool Cy_SysClk_PllLostLock(uint32_t clkPath)

Reports whether or not the selected PLL lost its lock since the last time this function was called.

Clears the lost lock indicator.

Function Usage

    /* Scenario: Suspicious change in Path 1 clock frequency was encountered
                 in the application. Check if the Path 1 PLL lost the lock. */

    if(Cy_SysClk_PllLostLock(1UL))
    {
        /* Insert error handling */
    }

Parameters

clkPath – Selects which PLL to check. 1 is the first PLL; 0 is invalid.

Returns

false = did not lose lock

true = lost lock

cy_en_sysclk_status_t Cy_SysClk_PllDisable(uint32_t clkPath)

Disables the selected PLL.

note

Call SystemCoreClockUpdate after this function calling if it affects the CLK_HF0 frequency.

note

Call Cy_SysLib_SetWaitStates before calling this function if the PLL is the source of CLK_HF0 and the CLK_HF0 frequency is increasing.

note

Call Cy_SysLib_SetWaitStates after calling this function if the PLL is the source of CLK_HF0 and the CLK_HF0 frequency is decreasing.

Side Effects

This function sets PLL bypass mode to CY_SYSCLK_FLLPLL_OUTPUT_INPUT. If AUTO mode should be used, call Cy_SysClk_PllConfigure or Cy_SysClk_PllManualConfigure before calling Cy_SysClk_PllEnable.

Function Usage

    /* Scenario: Path 1 PLL failed to enable and must be reconfigured. Or the
                 PLL is no longer used and hence needs to be disabled. */

    if (Cy_SysClk_PllIsEnabled(1UL))
    {
        if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllDisable(1UL))
        {
            /* Insert error handling */
        }
    }

    /* The clocks that relied on the PLL will now run off of the clock that
       was used to source the FLL (e.g. IMO or ECO). */

Parameters

clkPath – Selects which PLL to disable. 1 is the first PLL; 0 is invalid.

Returns

Error / status code:

CY_SYSCLK_SUCCESS - PLL successfully disabled

CY_SYSCLK_BAD_PARAM - invalid clock path number CY_SYSCLK_INVALID_STATE - ECO already enabled For the PSoC 64 devices there are possible situations when function returns the PRA error status code. This is because for PSoC 64 devices the function uses the PRA driver to change the protected registers. Refer to cy_en_pra_status_t for more details.

uint32_t Cy_SysClk_PllGetFrequency(uint32_t pll)

Returns the output frequency of the PLL.

note

If the return value equals zero, that means PLL is disabled.

Function Usage

    uint32_t freq = Cy_SysClk_PllGetFrequency(0UL);
    (void) freq; /* Supress 'unused variable' warning */

Parameters

pll – to get the frequency.

Returns

The output frequency of the path PLL.

void Cy_SysClk_IloEnable(void)

Enables the ILO.

note

The watchdog timer (WDT) must be unlocked before calling this function.

Function Usage

    /* Scenario: ILO needs to source the LFCLK. The watchdog timer (WDT) is unlocked
                 and all peripherals clocked using the LFCLK are disabled. */

    /* Enable the ILO */
    Cy_SysClk_IloEnable();

    /* Set the LFCLK source to the ILO */
    Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_ILO);

bool Cy_SysClk_IloIsEnabled(void)

Reports the Enabled/Disabled status of the ILO.

note

This API is available for CAT1A devices.

Function Usage

    /* Scenario: LFCLK needs to be sourced by the PILO instead of the ILO. All
                 peripherals clocked by the LFCLK are disabled and the Watchdog
                 timer (WDT) is unlocked. */

    if (Cy_SysClk_IloIsEnabled())
    {
        /* Disable the ILO */
        Cy_SysClk_IloDisable();

        /* Enable the PILO */
        Cy_SysClk_PiloEnable();

        /* Set the LFCLK source to the PILO */
        Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_PILO);
    }

Returns

Boolean status of ILO: true - Enabled, false - Disabled.

cy_en_sysclk_status_t Cy_SysClk_IloDisable(void)

Disables the ILO.

ILO can’t be disabled if WDT is enabled.

note

The watchdog timer (WDT) must be unlocked before calling this function. Do not call this function if the WDT is enabled, because the WDT is clocked by the ILO.

Function Usage

    /* Scenario: LFCLK needs to be sourced by the PILO instead of the ILO. All
                 peripherals clocked by the LFCLK are disabled and the Watchdog
                 timer (WDT) is unlocked. */

    if (Cy_SysClk_IloIsEnabled())
    {
        /* Disable the ILO */
        Cy_SysClk_IloDisable();

        /* Enable the PILO */
        Cy_SysClk_PiloEnable();

        /* Set the LFCLK source to the PILO */
        Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_PILO);
    }

Returns

Error / status code:

CY_SYSCLK_SUCCESS - ILO successfully disabled

CY_SYSCLK_INVALID_STATE - Cannot disable the ILO if the WDT is enabled. CY_SYSCLK_INVALID_STATE - ECO already enabled For the PSoC 64 devices there are possible situations when function returns the PRA error status code. This is because for PSoC 64 devices the function uses the PRA driver to change the protected registers. Refer to cy_en_pra_status_t for more details.

void Cy_SysClk_IloHibernateOn(bool on)

Controls whether the ILO stays on during a hibernate, or through an XRES or brown-out detect (BOD) event.

note

Writes to the register/bit are ignored if the watchdog (WDT) is locked.

Function Usage

    /* Scenario: The ILO needs to clock the Real-Time-clock (RTC) during chip
                 hibernate, hard reset (XRES) and Brown-out detect (BOD) events.
                 All peripherals clocked by the LFCLK are disabled and the
                 Watchdog timer (WDT) is unlocked. */

    /* Enable ILO operation during chip hibernate mode */
    Cy_SysClk_IloHibernateOn(true);

    /* Enable the ILO */
    Cy_SysClk_IloEnable();

    /* Set the LFCLK source to the ILO */
    Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_ILO);

Parameters

on

true = ILO stays on during hibernate or across XRES/BOD.

false = ILO turns off for hibernate or XRES/BOD.

void Cy_SysClk_PiloEnable(void)

Enables the PILO.

note

This function blocks for 1 millisecond between enabling the PILO and releasing the PILO reset.

Function Usage

    /* Scenario: PILO needs to source the LFCLK.  All peripherals clocked by
                 the LFCLK are disabled and the Watchdog timer (WDT) is unlocked. */

    /* Enable the PILO. Note: Blocks for 1 millisecond. */
    Cy_SysClk_PiloEnable();

    /* Set the LFCLK source to the PILO */
    Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_PILO);

bool Cy_SysClk_PiloIsEnabled(void)

Reports the Enabled/Disabled status of the PILO.

note

This API is available for CAT1A devices.

Function Usage

    /* Scenario: LFCLK needs to be sourced by the ILO instead of the PILO. All
                 peripherals clocked by the LFCLK are disabled and the Watchdog
                 timer (WDT) is unlocked. */

    if (Cy_SysClk_PiloIsEnabled())
    {
        /* Disable the PILO */
        Cy_SysClk_PiloDisable();

        /* Enable the ILO */
        Cy_SysClk_IloEnable();

        /* Set the LFCLK source to the ILO */
        Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_ILO);
    }

Returns

Boolean status of PILO: true - Enabled, false - Disabled.

void Cy_SysClk_PiloDisable(void)

Disables the PILO.

Function Usage

    /* Scenario: LFCLK needs to be sourced by the ILO instead of the PILO. All
                 peripherals clocked by the LFCLK are disabled and the Watchdog
                 timer (WDT) is unlocked. */

    if (Cy_SysClk_PiloIsEnabled())
    {
        /* Disable the PILO */
        Cy_SysClk_PiloDisable();

        /* Enable the ILO */
        Cy_SysClk_IloEnable();

        /* Set the LFCLK source to the ILO */
        Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_ILO);
    }

void Cy_SysClk_PiloSetTrim(uint32_t trimVal)

Sets the PILO trim bits, which adjusts the PILO frequency.

This is typically done after measuring the PILO frequency; see Cy_SysClk_StartClkMeasurementCounters().

Function Usage

    /* Scenario: PILO needs to be trimmed to +/- 2% of nominal 32.768 kHz using
                 the ECO as the source. */

    #define ECO_FREQ        24000000UL  /* 24 MHz ECO */
    #define PILO_NOMINAL    32768UL     /* 32.768 kHz PILO */
    #define PILO_ACCURACY   655UL       /* PILO_NOMINAL * 0.02 */

    bool trimStatus = false;

    while(!trimStatus)
    {
        /* Start the PILO clock measurement using the IMO */
        (void)Cy_SysClk_StartClkMeasurementCounters(CY_SYSCLK_MEAS_CLK_PILO,    /* Counter 1 clock      = PILO */
                                                    0x3FFUL,                    /* Counter 1 init value = 1024 */
                                                    CY_SYSCLK_MEAS_CLK_ECO);    /* Counter 2 clock      = ECO  */
        /* Wait for counter 1 to reach 0 */
        while (!Cy_SysClk_ClkMeasurementCountersDone()){}

        /* Measure clock 1 with the ECO clock cycles (counter 2) */
        uint32_t measuredFreq = Cy_SysClk_ClkMeasurementCountersGetFreq(false, ECO_FREQ);

        /* Increment/decrement the trim depending on the returned result */
        if ((PILO_NOMINAL + PILO_ACCURACY) < measuredFreq)
        {
            Cy_SysClk_PiloSetTrim(Cy_SysClk_PiloGetTrim() - 1UL);
        }
        else if (measuredFreq < (PILO_NOMINAL - PILO_ACCURACY))
        {
            Cy_SysClk_PiloSetTrim(Cy_SysClk_PiloGetTrim() + 1UL);
        }
        else
        {
            /* Trimmed within limits */
            trimStatus = true;
        }
    }

uint32_t Cy_SysClk_PiloGetTrim(void)

Reports the current PILO trim bits value.

Function Usage

    /* Scenario: PILO needs to be trimmed to +/- 2% of nominal 32.768 kHz using
                 the ECO as the source. */

    #define ECO_FREQ        24000000UL  /* 24 MHz ECO */
    #define PILO_NOMINAL    32768UL     /* 32.768 kHz PILO */
    #define PILO_ACCURACY   655UL       /* PILO_NOMINAL * 0.02 */

    bool trimStatus = false;

    while(!trimStatus)
    {
        /* Start the PILO clock measurement using the IMO */
        (void)Cy_SysClk_StartClkMeasurementCounters(CY_SYSCLK_MEAS_CLK_PILO,    /* Counter 1 clock      = PILO */
                                                    0x3FFUL,                    /* Counter 1 init value = 1024 */
                                                    CY_SYSCLK_MEAS_CLK_ECO);    /* Counter 2 clock      = ECO  */
        /* Wait for counter 1 to reach 0 */
        while (!Cy_SysClk_ClkMeasurementCountersDone()){}

        /* Measure clock 1 with the ECO clock cycles (counter 2) */
        uint32_t measuredFreq = Cy_SysClk_ClkMeasurementCountersGetFreq(false, ECO_FREQ);

        /* Increment/decrement the trim depending on the returned result */
        if ((PILO_NOMINAL + PILO_ACCURACY) < measuredFreq)
        {
            Cy_SysClk_PiloSetTrim(Cy_SysClk_PiloGetTrim() - 1UL);
        }
        else if (measuredFreq < (PILO_NOMINAL - PILO_ACCURACY))
        {
            Cy_SysClk_PiloSetTrim(Cy_SysClk_PiloGetTrim() + 1UL);
        }
        else
        {
            /* Trimmed within limits */
            trimStatus = true;
        }
    }

uint32_t Cy_SysClk_AltHfGetFrequency(void)

Reports the frequency of the Alternative High-Frequency Clock.

Function Usage

    /* BLE ECO configuration: ECO Frequency: 32 MHZ, Divider: 2 */
    /* Start-up time(uS): 1500, Load cap(pF): 9.9 */
    
    uint32_t startTime = (uint32_t)(1500 / 31.25);
    uint32_t loadCap   = (uint32_t)((9.9 - 7.5) / 0.075);
    
    /* Configure the BLE ECO clock */
    (void) Cy_BLE_EcoConfigure(CY_BLE_BLESS_ECO_FREQ_32MHZ, CY_BLE_SYS_ECO_CLK_DIV_2, loadCap, startTime, CY_BLE_ECO_VOLTAGE_REG_AUTO);
    
    /* In case if there is a need to get the BLE ECO frequency */
    uint32_t bleEcoFreq = Cy_SysClk_AltHfGetFrequency();

cy_en_sysclk_status_t Cy_SysClk_StartClkMeasurementCounters(cy_en_meas_clks_t clock1, uint32_t count1, cy_en_meas_clks_t clock2)

Assigns clocks to the clock measurement counters, and starts counting.

The counters let you measure a clock frequency using another clock as a reference. There are two counters.

  • One counter (counter1), which is clocked by clock1, is loaded with an initial value and counts down to zero.

  • The second counter (counter2), which is clocked by clock2, counts up until the first counter reaches zero.

Either clock1 or clock2 can be a reference clock; the other clock becomes the measured clock. The reference clock frequency is always known.

After calling this function, call

Cy_SysClk_ClkMeasurementCountersDone() to determine when counting is done; that is, counter1 has counted down to zero. Then call Cy_SysClk_ClkMeasurementCountersGetFreq() to calculate the frequency of the measured clock.

note

The counters are both 24-bit, so the maximum value of count1 is 0xFFFFFF. If clock2 frequency is greater than clock1, make sure that count1 is low enough that counter2 does not overflow before counter1 reaches zero.

note

The time to complete a measurement is count1 / clock1 frequency.

note

The clocks for both counters must have a nonzero frequency, or Cy_SysClk_ClkMeasurementCountersGetFreq() incorrectly reports the result of the previous measurement.

note

Do not enter a device low power mode (Sleep, Deep Sleep) while doing a measurement; the measured clock frequency may not be accurate.

Function Usage

    /* Scenario: ILO frequency may be drifting. Measure the ILO frequency using
                 the clock measurement counters, with the IMO as the reference. */

    #define  IMO_FREQ       8000000UL   /* 8 MHz IMO */
    #define  ILO_NOMINAL    32768UL     /* 32.768 kHz ILO */

    /* Start the ILO clock measurement using the IMO */
    (void)Cy_SysClk_StartClkMeasurementCounters(CY_SYSCLK_MEAS_CLK_ILO,     /* Counter 1 clock  = ILO */
                                                0x7FUL,                     /* Counter 1 period = 128 */
                                                CY_SYSCLK_MEAS_CLK_IMO);    /* Counter 2 clock  = IMO */
    /* Wait for counter 1 to reach 0 */
    while(!Cy_SysClk_ClkMeasurementCountersDone()){}

    /* Measure clock 1 with the IMO clock cycles (counter 2) */
    uint32_t measuredFreq = Cy_SysClk_ClkMeasurementCountersGetFreq(false, IMO_FREQ);

    if(measuredFreq != ILO_NOMINAL)
    {
        /* Take appropriate action such as trimming the ILO or changing the LFCLK source */
    }

Parameters
  • clock1 – The clock for counter1

  • count1 – The initial value for counter1, from which counter1 counts down to zero.

  • clock2 – The clock for counter2

Returns

Error / status code:

CY_SYSCLK_INVALID_STATE if already doing a measurement

CY_SYSCLK_BAD_PARAM if invalid clock input parameter

else CY_SYSCLK_SUCCESS CY_SYSCLK_INVALID_STATE - ECO already enabled For the PSoC 64 devices there are possible situations when function returns the PRA error status code. This is because for PSoC 64 devices the function uses the PRA driver to change the protected registers. Refer to

cy_en_pra_status_t for more details.

uint32_t Cy_SysClk_ClkMeasurementCountersGetFreq(bool measuredClock, uint32_t refClkFreq)

Calculates the frequency of the indicated measured clock (clock1 or clock2).

  • If clock1 is the measured clock, its frequency is: clock1 frequency = (count1 / count2) * clock2 frequency

  • If clock2 is the measured clock, its frequency is: clock2 frequency = (count2 / count1) * clock1 frequency

Call this function only after counting is done; see Cy_SysClk_ClkMeasurementCountersDone().

warning

The function returns zero, if during measurement device was in the Deep Sleep or partially blocking flash operation occurred. It means that current measurement is not valid and you should call the Cy_SysClk_StartClkMeasurementCounters() function once again.

Function Usage

Refer to the Cy_SysClk_StartClkMeasurementCounters() function usage.

Parameters
  • measuredClock – False (0) if the measured clock is clock1; true (1) if the measured clock is clock2.

  • refClkFreq – The reference clock frequency (clock1 or clock2).

Returns

The frequency of the measured clock, in Hz.

bool Cy_SysClk_ClkMeasurementCountersDone(void)

Checks if clock measurement counting is done, that is, counter1 has counted down to zero.

Call Cy_SysClk_StartClkMeasurementCounters() before calling this function.

Function Usage

Refer to the Cy_SysClk_StartClkMeasurementCounters() function usage.

Returns

Status of calibration counters:

true = done

false = not done

int32_t Cy_SysClk_IloTrim(uint32_t iloFreq)

Trims the ILO to be as close to 32,768 Hz as possible.

note

The watchdog timer (WDT) must be unlocked before calling this function.

Function Usage

    /* Scenario: ILO needs to be trimmed to +/- 1.5% of nominal 32.768 kHz using
                 the IMO. The WDT is unlocked and all peripherals clocked using
                 the ILO are disabled. */

    #define  IMO_FREQ       8000000UL   /* 8 MHz IMO */

    /* Start the ILO clock measurement using the IMO */
    (void)Cy_SysClk_StartClkMeasurementCounters(CY_SYSCLK_MEAS_CLK_ILO,     /* Counter 1 clock  = ILO */
                                                0x7FUL,                     /* Counter 1 period = 128 */
                                                CY_SYSCLK_MEAS_CLK_IMO);    /* Counter 2 clock  = IMO */
    /* Wait for counter 1 to reach 0 */
    while(!Cy_SysClk_ClkMeasurementCountersDone()){}

    /* Measure clock 1 with the IMO clock cycles (counter 2) */
    uint32_t measuredFreq = Cy_SysClk_ClkMeasurementCountersGetFreq(false, IMO_FREQ);

    /* Attempt to trim the ILO by 1 iteration step */
    int32_t trimDelta = Cy_SysClk_IloTrim(measuredFreq);

    if(0 != trimDelta)
    {
        /* Not yet trimmed to 1.5% of nominal 32.768 kHz. Repeat measurement and trim. */
    }

Parameters

iloFreq – current ILO frequency. Call Cy_SysClk_StartClkMeasurementCounters and other measurement functions to obtain the current frequency of the ILO.

Returns

Change in trim value - 0 if done; that is, no change in trim value.

int32_t Cy_SysClk_PiloTrim(uint32_t piloFreq)

Trims the PILO to be as close to 32,768 Hz as possible.

Function Usage

    /* Scenario: PILO needs to be trimmed to +/-250 ppm of nominal 32.768 kHz
    All peripherals clocked using the PILO are disabled. */
    #define  ECO_FREQ       24000000UL   /* 24 MHz ECO */

#ifdef CY_IP_MXBLESS
    /* Call PILO Initial trim */
    Cy_SysClk_PiloInitialTrim();

    /* Find out and store step size into stepSize variable */
    Cy_SysClk_PiloUpdateTrimStep();
#endif /* CY_IP_MXBLESS */

    /* Start the PILO clock measurement using the ECO */
    (void)Cy_SysClk_StartClkMeasurementCounters(CY_SYSCLK_MEAS_CLK_PILO,    /* Counter 1 clock  = PILO     */
                                                0x3FFUL,                    /* Counter 1 init value = 1024 */
                                                CY_SYSCLK_MEAS_CLK_ECO);    /* COunter 2 clock  = ECO      */
    /* Wait for counter 1 to reach 0 */
    while (!Cy_SysClk_ClkMeasurementCountersDone()){}

    /* Measure clock 1 with the ECO clock cycles (counter 2) */
    uint32_t measuredFreq = Cy_SysClk_ClkMeasurementCountersGetFreq(false, ECO_FREQ);

    uint32_t trimDelta;

    do
    {
        /* Attempt to trim the PILO with calculated stepSize via */
        trimDelta = Cy_SysClk_PiloTrim(measuredFreq);
    }while (0UL != trimDelta);

Parameters

piloFreq – current PILO frequency. Call Cy_SysClk_StartClkMeasurementCounters and other measurement functions to obtain the current frequency of the PILO.

Returns

Change in trim value; 0 if done, that is, no change in trim value.

void Cy_SysClk_PiloInitialTrim(void)

Initial trims the PILO to be as close to 32,768 Hz as possible.

This function takes ECO ALTHF as reference clock and calculate Fine PILO frequency trimming, by using binary search algorithm.

This function requires configured BLE ECO ALTHF clock. Use ModusToolbox Device Configurator to configure BLE ECO ALTHF clock.

note

This function must be call after every power-up.

note

The function is applicable only for a PSoC 6 BLE devices.

Function Usage


    /* Perform initial PILO trimming and update the trim step size. 
     * \note:
     * 1. Call those functions after every power-up.
     * 2. Those functions require a configured BLE ECO ALTHF clock. 
     *    Use ModusToolbox Device Configurator to configure the BLE ECO BLE ECO ALTHF
     *    clock. The recommended frequency is 16 Mhz. */    
    Cy_SysClk_PiloInitialTrim();
    Cy_SysClk_PiloUpdateTrimStep();

void Cy_SysClk_PiloUpdateTrimStep(void)

Calculates and updates the PILO trim step size (stepSize variable).

The stepSize value is used by Cy_SysClk_PiloTrim function during periodical PILO calibration.

This function requires configured BLE ECO ALTHF clock. Use ModusToolbox Device Configurator to configure BLE ECO ALTHF clock.

note

This function must be call after every power-up after call of Cy_SysClk_PiloInitialTrim function.

note

To achieve best trimming results it is recommended to configure BLE ECO ALTHF reference clock to 16 MHz.

note

The function is applicable only for a PSoC 6 BLE devices.

Function Usage


    /* Perform initial PILO trimming and update the trim step size. 
     * \note:
     * 1. Call those functions after every power-up.
     * 2. Those functions require a configured BLE ECO ALTHF clock. 
     *    Use ModusToolbox Device Configurator to configure the BLE ECO BLE ECO ALTHF
     *    clock. The recommended frequency is 16 Mhz. */    
    Cy_SysClk_PiloInitialTrim();
    Cy_SysClk_PiloUpdateTrimStep();

cy_en_syspm_status_t Cy_SysClk_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams, cy_en_syspm_callback_mode_t mode)

Callback function to be used when entering system Deep Sleep mode.

This function is applicable if:

  • The FLL is enabled

  • The PLL is enabled and is driven by ECO

This function performs the following:

  1. Before entering Deep Sleep, the clock configuration is saved in SRAM. If the FLL/PLL source is the ECO, then the FLL/PLL is bypassed and the source is changed to IMO.

    If the FLL is enabled - it is just bypassed.

  2. Upon wakeup from Deep Sleep, the function waits for ECO stabilization, then restores the configuration and waits for the FLL/PLL to regain their frequency locks.

    If ECO is not used and FLL is enabled - it waits for FLL lock and unbypasses it.

The function prevents entry into Deep Sleep mode if the measurement counters are currently counting; see Cy_SysClk_StartClkMeasurementCounters.

This function can be called during execution of Cy_SysPm_CpuEnterDeepSleep. To do so, register this function as a callback before calling Cy_SysPm_CpuEnterDeepSleep - specify CY_SYSPM_DEEPSLEEP as the callback type and call Cy_SysPm_RegisterCallback.

note

This function is recommended to be the last callback that is registered. Doing so minimizes the time spent on low power mode entry and exit.
This function implements all four SysPm callback modes cy_en_syspm_callback_mode_t. So the cy_stc_syspm_callback_t::skipMode must be set to 0UL.
This function does not support such cases as, for example, FLL is enabled but bypassed by user code before entering Deep Sleep.
You can use this callback implementation as an example to design custom low-power callbacks for certain user application.

Function Usage

    /* Scenario: The application uses FLL/PLL sourced from the ECO. The device
                 needs to enter chip Deep Sleep. The ECO and FLL/PLL must be
                 suitably prepared before entering low power mode. */

    /* Register all the Deep Sleep callbacks for other peripherals.
       The SysClk callback is recommended to be registered last to minimize
       the low power mode entry and wakeup timings. */

    cy_stc_syspm_callback_params_t clkCallbackParams = {
        /*.base       =*/ NULL,
        /*.context    =*/ NULL
    };

    cy_stc_syspm_callback_t clkCallback = {
        /*.callback       =*/ &Cy_SysClk_DeepSleepCallback,
        /*.type           =*/ CY_SYSPM_DEEPSLEEP,
        /*.skipMode       =*/ 0UL,
        /*.callbackParams =*/ &clkCallbackParams,
        /*.prevItm        =*/ NULL,
        /*.nextItm        =*/ NULL,
        /*.order          =*/ 0
    };

    /* Register the clock callback */
    if(!Cy_SysPm_RegisterCallback(&clkCallback))
    {
        /* Could not register callback. Examine the number of registered callbacks */
    }

    /* Ensure that the clock measurement is not running and enter chip Deep Sleep */

Parameters
Returns

Error / status code; see cy_en_syspm_status_t. Pass if not doing a clock measurement, otherwise Fail. Timeout if timeout waiting for ECO, FLL or PLL to get stable / regain its frequency lock. CY_SYSCLK_INVALID_STATE - ECO already enabled For the PSoC 64 devices there are possible situations when function returns the PRA error status code. This is because for PSoC 64 devices the function uses the PRA driver to change the protected registers. Refer to cy_en_pra_status_t for more details.

cy_en_sysclk_status_t Cy_SysClk_WcoEnable(uint32_t timeoutus)

Enables the WCO.

Function Usage

    /* Scenario: The WCO needs to source the backup clock for the real-time clock
                 operation. Timeout of 2ms is tolerable. The WCO pins are configured
                 using the gpio driver(SRSS_WCO_IN_PIN, SRSS_WCO_OUT_PIN). */

    /* Enable the WCO with a timeout of 2000 microseconds */
    if(CY_SYSCLK_SUCCESS != Cy_SysClk_WcoEnable(2000))
    {
        /* Insert error handling */
    }

    /* Set the backup clock source to WCO */
    Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_WCO);

Parameters

timeoutus – amount of time in microseconds to wait for the WCO to be ready. If WCO is not ready, WCO is stopped. To avoid waiting for WCO ready set this to 0, and manually check if WCO is okay using Cy_SysClk_WcoOkay.

Returns

Error / status code:

CY_SYSCLK_SUCCESS - WCO successfully enabled

CY_SYSCLK_TIMEOUT - Timeout waiting for WCO to stabilize CY_SYSCLK_INVALID_STATE - ECO already enabled For the PSoC 64 devices there are possible situations when function returns the PRA error status code. This is because for PSoC 64 devices the function uses the PRA driver to change the protected registers. Refer to cy_en_pra_status_t for more details.

bool Cy_SysClk_WcoOkay(void)

Reports the status of the WCO_OK bit.

Function Usage

    /* Scenario: The WCO needs to source the backup clock for the real-time
                 clock operation. It needs to be enabled in a non-blocking
                 manner. The WCO pins are configured using the gpio driver
                 (SRSS_WCO_IN_PIN, SRSS_WCO_OUT_PIN). */

    /* Enable the WCO without timeout */
    (void)Cy_SysClk_WcoEnable(0UL);
    while(!Cy_SysClk_WcoOkay())
    {
        /* WCO is not yet ready. Perform some other operation. */
    }

    /* Set the backup clock source to WCO */
    Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_WCO);

Returns

true = okay

false = not okay

void Cy_SysClk_WcoDisable(void)

Disables the WCO.

Function Usage

    /* Scenario: LFCLK needs to be sourced by the PILO instead of the WCO. All
                 peripherals clocked by the LFCLK are disabled and the Watchdog
                 timer (WDT) is unlocked. */

    /* Disable the WCO */
    Cy_SysClk_WcoDisable();

    /* Enable the PILO */
    Cy_SysClk_PiloEnable();

    /* Set the LFCLK source to the PILO */
    Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_PILO);

void Cy_SysClk_WcoBypass(cy_en_wco_bypass_modes_t bypass)

Sets whether the WCO is bypassed or not.

If it is bypassed, then a 32-kHz clock must be provided on the wco_out pin.

Function Usage

    /* Scenario: An external watch crystal oscillator needs to be connected to
                 the WCO pins instead of a watch crystal. This signal needs
                 to source the backup clock for the real-time clock operation.
                 The WCO pins are configured using the gpio driver
                 (SRSS_WCO_IN_PIN, SRSS_WCO_OUT_PIN). */

    /* WCO bypassed mode - 32768 kHz square-wave supplied through SRSS_WCO_OUT_PIN pin */
    Cy_SysClk_WcoBypass(CY_SYSCLK_WCO_BYPASSED);

    /* Enable the WCO with a timeout of 2000 microsecond */
    if(CY_SYSCLK_SUCCESS != Cy_SysClk_WcoEnable(2000UL))
    {
        /* Insert error handling */
    }

    /* Set the backup clock source to WCO */
    Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_WCO);

Parameters

bypasscy_en_wco_bypass_modes_t

void Cy_SysClk_MfoEnable(bool deepSleepEnable)

Enables the MFO.

Function Usage

    /* Scenario: MFO is needed to source LCD with 1MHz in Deep Sleep mode. */

    Cy_SysClk_MfoEnable(true); /* Enable MFO with Deep Sleep operation */

    if (Cy_SysClk_ClkMfIsEnabled()) /* If CLK_MF is already enabled */
    {
        Cy_SysClk_ClkMfDisable();   /* Disable CLK_MF */
    }

    if (2UL != Cy_SysClk_ClkMfGetDivider()) /* Check the divider */
    {
        Cy_SysClk_ClkMfSetDivider(2UL); /* Set CLK_MF divider */
    }

    Cy_SysClk_ClkMfEnable();        /* Enable CLK_MF */

    /* Check the CLK_MF frequency */
    uint32_t clkMfreq = Cy_SysClk_ClkMfGetFrequency();

Parameters

deepSleepEnable – enables MFO operation is Deep Sleep low power mode.

bool Cy_SysClk_MfoIsEnabled(void)

Reports whether MFO is enabled or not.

Function Usage

    /* Scenario: MFO is not more needed so could be disabled. */

    Cy_SysClk_ClkMfDisable(); /* Disable CLK_MF */

    if (Cy_SysClk_MfoIsEnabled()) /* If MFO enabled */
    {
        Cy_SysClk_MfoDisable(); /* Disable MF0 */
    }

Returns

false - disabled

true - enabled

void Cy_SysClk_MfoDisable(void)

Disables the MFO.

Function Usage

    /* Scenario: MFO is not more needed so could be disabled. */

    Cy_SysClk_ClkMfDisable(); /* Disable CLK_MF */

    if (Cy_SysClk_MfoIsEnabled()) /* If MFO enabled */
    {
        Cy_SysClk_MfoDisable(); /* Disable MF0 */
    }

void Cy_SysClk_ClkMfEnable(void)

Enables the CLK_MF.

Function Usage

    /* Scenario: MFO is needed to source LCD with 1MHz in Deep Sleep mode. */

    Cy_SysClk_MfoEnable(true); /* Enable MFO with Deep Sleep operation */

    if (Cy_SysClk_ClkMfIsEnabled()) /* If CLK_MF is already enabled */
    {
        Cy_SysClk_ClkMfDisable();   /* Disable CLK_MF */
    }

    if (2UL != Cy_SysClk_ClkMfGetDivider()) /* Check the divider */
    {
        Cy_SysClk_ClkMfSetDivider(2UL); /* Set CLK_MF divider */
    }

    Cy_SysClk_ClkMfEnable();        /* Enable CLK_MF */

    /* Check the CLK_MF frequency */
    uint32_t clkMfreq = Cy_SysClk_ClkMfGetFrequency();

bool Cy_SysClk_ClkMfIsEnabled(void)

Reports whether CLK_MF is enabled or not.

Function Usage

    /* Scenario: MFO is needed to source LCD with 1MHz in Deep Sleep mode. */

    Cy_SysClk_MfoEnable(true); /* Enable MFO with Deep Sleep operation */

    if (Cy_SysClk_ClkMfIsEnabled()) /* If CLK_MF is already enabled */
    {
        Cy_SysClk_ClkMfDisable();   /* Disable CLK_MF */
    }

    if (2UL != Cy_SysClk_ClkMfGetDivider()) /* Check the divider */
    {
        Cy_SysClk_ClkMfSetDivider(2UL); /* Set CLK_MF divider */
    }

    Cy_SysClk_ClkMfEnable();        /* Enable CLK_MF */

    /* Check the CLK_MF frequency */
    uint32_t clkMfreq = Cy_SysClk_ClkMfGetFrequency();

Returns

false - disabled

true - enabled

void Cy_SysClk_ClkMfDisable(void)

Disables the CLK_MF.

Function Usage

    /* Scenario: MFO is not more needed so could be disabled. */

    Cy_SysClk_ClkMfDisable(); /* Disable CLK_MF */

    if (Cy_SysClk_MfoIsEnabled()) /* If MFO enabled */
    {
        Cy_SysClk_MfoDisable(); /* Disable MF0 */
    }

void Cy_SysClk_ClkMfSetDivider(uint32_t divider)

Sets the clock divider for CLK_MF.

Precondition

If the CLK_MF is already enabled - it should be disabled prior to use this function by Cy_SysClk_ClkMfDisable.

Function Usage

    /* Scenario: MFO is needed to source LCD with 1MHz in Deep Sleep mode. */

    Cy_SysClk_MfoEnable(true); /* Enable MFO with Deep Sleep operation */

    if (Cy_SysClk_ClkMfIsEnabled()) /* If CLK_MF is already enabled */
    {
        Cy_SysClk_ClkMfDisable();   /* Disable CLK_MF */
    }

    if (2UL != Cy_SysClk_ClkMfGetDivider()) /* Check the divider */
    {
        Cy_SysClk_ClkMfSetDivider(2UL); /* Set CLK_MF divider */
    }

    Cy_SysClk_ClkMfEnable();        /* Enable CLK_MF */

    /* Check the CLK_MF frequency */
    uint32_t clkMfreq = Cy_SysClk_ClkMfGetFrequency();

Parameters

divider – divider value between 1 and 256.

uint32_t Cy_SysClk_ClkMfGetDivider(void)

Returns the clock divider of CLK_MF.

Function Usage

    /* Scenario: MFO is needed to source LCD with 1MHz in Deep Sleep mode. */

    Cy_SysClk_MfoEnable(true); /* Enable MFO with Deep Sleep operation */

    if (Cy_SysClk_ClkMfIsEnabled()) /* If CLK_MF is already enabled */
    {
        Cy_SysClk_ClkMfDisable();   /* Disable CLK_MF */
    }

    if (2UL != Cy_SysClk_ClkMfGetDivider()) /* Check the divider */
    {
        Cy_SysClk_ClkMfSetDivider(2UL); /* Set CLK_MF divider */
    }

    Cy_SysClk_ClkMfEnable();        /* Enable CLK_MF */

    /* Check the CLK_MF frequency */
    uint32_t clkMfreq = Cy_SysClk_ClkMfGetFrequency();

Returns

divider value in range 1..256.

uint32_t Cy_SysClk_ClkMfGetFrequency(void)

Reports the output clock signal frequency of CLK_MF.

Function Usage

    /* Scenario: MFO is needed to source LCD with 1MHz in Deep Sleep mode. */

    Cy_SysClk_MfoEnable(true); /* Enable MFO with Deep Sleep operation */

    if (Cy_SysClk_ClkMfIsEnabled()) /* If CLK_MF is already enabled */
    {
        Cy_SysClk_ClkMfDisable();   /* Disable CLK_MF */
    }

    if (2UL != Cy_SysClk_ClkMfGetDivider()) /* Check the divider */
    {
        Cy_SysClk_ClkMfSetDivider(2UL); /* Set CLK_MF divider */
    }

    Cy_SysClk_ClkMfEnable();        /* Enable CLK_MF */

    /* Check the CLK_MF frequency */
    uint32_t clkMfreq = Cy_SysClk_ClkMfGetFrequency();

Returns

The frequency, in Hz.

cy_en_sysclk_status_t Cy_SysClk_ClkHfEnable(uint32_t clkHf)

Enables the selected clkHf.

Function Usage

    /* Scenario: ECO needs to source HFCLK2 through Path 2. The ECO is
                 configured through its function calls. */

    #define CLKPATH2 (2UL)
    #define HFCLK2 (2UL)

    uint32_t clkPathMuxFreq = 0UL; /* Variable to store the Clock Path Mux output frequency */

    /* Set the clock path 2 mux to be sourced from ECO */
    if(CY_SYSCLK_SUCCESS == Cy_SysClk_ClkPathSetSource(CLKPATH2, CY_SYSCLK_CLKPATH_IN_ECO))
    {
        clkPathMuxFreq = Cy_SysClk_ClkPathMuxGetFrequency(CLKPATH2);
        /* Now clkPathMuxFreq contains the Clock Path Mux output frequency */
    }
    else
    {
        /* Perform error handling */
    }

    /* Set the HFCLK2 source to clock path 2 and enable HFCLK2 */
    (void)Cy_SysClk_ClkHfSetSource(HFCLK2, CY_SYSCLK_CLKHF_IN_CLKPATH2);

    /* Enable HFCLK2  */
    (void)Cy_SysClk_ClkHfEnable(HFCLK2);

Parameters

clkHf – Selects which clkHf to enable.

Returns

cy_en_sysclk_status_t CY_SYSCLK_INVALID_STATE - ECO already enabled For the PSoC 64 devices there are possible situations when function returns the PRA error status code. This is because for PSoC 64 devices the function uses the PRA driver to change the protected registers. Refer to cy_en_pra_status_t for more details.

bool Cy_SysClk_ClkHfIsEnabled(uint32_t clkHf)

Reports the Enabled/Disabled status of clkHf.

note

This API is available for CAT1A devices.

Function Usage

    /* Scenario: HFCLK1 is no longer required in the application and can be
                 switched off.
       Note:     HFCLK0 cannot be disabled */

    #define HFCLK1 (1UL)

    if (Cy_SysClk_ClkHfIsEnabled(HFCLK1))
    {
        /* Disable HFCLK1 */
        (void)Cy_SysClk_ClkHfDisable(HFCLK1);
    }

Parameters

clkHf – Selects which clkHf to check.

Returns

Boolean status of clkHf: true - Enabled, false - Disabled.

cy_en_sysclk_status_t Cy_SysClk_ClkHfDisable(uint32_t clkHf)

Disables the selected clkHf.

note

clkHf[0] cannot be disabled.

Function Usage

    /* Scenario: HFCLK1 is no longer required in the application and can be
                 switched off.
       Note:     HFCLK0 cannot be disabled */

    #define HFCLK1 (1UL)

    if (Cy_SysClk_ClkHfIsEnabled(HFCLK1))
    {
        /* Disable HFCLK1 */
        (void)Cy_SysClk_ClkHfDisable(HFCLK1);
    }

Parameters

clkHf – Selects which clkHf to enable.

Returns

cy_en_sysclk_status_t

cy_en_sysclk_status_t Cy_SysClk_ClkHfSetSource(uint32_t clkHf, cy_en_clkhf_in_sources_t source)

Selects the source of the selected clkHf.

note

Call SystemCoreClockUpdate after this function calling if it affects the CLK_HF0 frequency.

note

Call Cy_SysLib_SetWaitStates before calling this function if CLK_HF0 frequency is increasing.

note

Call Cy_SysLib_SetWaitStates after calling this function if CLK_HF0 frequency is decreasing.

Function Usage

    /* Scenario: HFCLK1 source may have been updated to Path 0 somewhere in the
                 application. Check if it was and change the source to Path 1. */

    if(CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(1UL))
    {
        /* Set the HFCLK1 source to Path 1 clock */
        (void)Cy_SysClk_ClkHfDisable(1UL);
        (void)Cy_SysClk_ClkHfSetSource(1UL, CY_SYSCLK_CLKHF_IN_CLKPATH1);
        (void)Cy_SysClk_ClkHfEnable(1UL);
    }

Parameters
Returns

cy_en_sysclk_status_t CY_SYSCLK_INVALID_STATE - ECO already enabled For the PSoC 64 devices there are possible situations when function returns the PRA error status code. This is because for PSoC 64 devices the function uses the PRA driver to change the protected registers. Refer to cy_en_pra_status_t for more details.

cy_en_clkhf_in_sources_t Cy_SysClk_ClkHfGetSource(uint32_t clkHf)

Reports the source of the selected clkHf.

Function Usage

    /* Scenario: HFCLK1 source may have been updated to Path 0 somewhere in the
                 application. Check if it was and change the source to Path 1. */

    if(CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(1UL))
    {
        /* Set the HFCLK1 source to Path 1 clock */
        (void)Cy_SysClk_ClkHfDisable(1UL);
        (void)Cy_SysClk_ClkHfSetSource(1UL, CY_SYSCLK_CLKHF_IN_CLKPATH1);
        (void)Cy_SysClk_ClkHfEnable(1UL);
    }

Parameters

clkHf – selects which clkHf to get the source of.

Returns

cy_en_clkhf_in_sources_t

cy_en_sysclk_status_t Cy_SysClk_ClkHfSetDivider(uint32_t clkHf, cy_en_clkhf_dividers_t divider)

Sets the pre-divider for a clkHf.

note

Also call Cy_SysClk_ClkHfSetSource to set the clkHf source.

note

Call SystemCoreClockUpdate after this function calling if it affects the CLK_HF0 frequency.

note

Call Cy_SysLib_SetWaitStates before calling this function if CLK_HF0 frequency is increasing.

note

Call Cy_SysLib_SetWaitStates after calling this function if CLK_HF0 frequency is decreasing.

Function Usage

    /* Scenario: Set HFCLK0 divider to 8, to reduce frequency and save power */

    if(CY_SYSCLK_CLKHF_DIVIDE_BY_8 != Cy_SysClk_ClkHfGetDivider(0UL))
    {
        /* Set the HFCLK0 divider to 8 */
        (void)Cy_SysClk_ClkHfSetDivider(0UL, CY_SYSCLK_CLKHF_DIVIDE_BY_8);
    }

    /* Check the HFCLK0 frequency */
    uint32_t clkHf0freq = Cy_SysClk_ClkHfGetFrequency(0UL);

Parameters
Returns

cy_en_sysclk_status_t CY_SYSCLK_INVALID_STATE - ECO already enabled For the PSoC 64 devices there are possible situations when function returns the PRA error status code. This is because for PSoC 64 devices the function uses the PRA driver to change the protected registers. Refer to cy_en_pra_status_t for more details.

cy_en_clkhf_dividers_t Cy_SysClk_ClkHfGetDivider(uint32_t clkHf)

Reports the pre-divider value for a clkHf.

Function Usage

    /* Scenario: Set HFCLK0 divider to 8, to reduce frequency and save power */

    if(CY_SYSCLK_CLKHF_DIVIDE_BY_8 != Cy_SysClk_ClkHfGetDivider(0UL))
    {
        /* Set the HFCLK0 divider to 8 */
        (void)Cy_SysClk_ClkHfSetDivider(0UL, CY_SYSCLK_CLKHF_DIVIDE_BY_8);
    }

    /* Check the HFCLK0 frequency */
    uint32_t clkHf0freq = Cy_SysClk_ClkHfGetFrequency(0UL);

Parameters

clkHf – selects which clkHf to check divider of.

Returns

cy_en_clkhf_dividers_t

uint32_t Cy_SysClk_ClkHfGetFrequency(uint32_t clkHf)

Reports the frequency of the selected clkHf.

note

The reported frequency may be zero, which indicates unknown. This happens if the source input is dsi_out or clk_altlf.

Function Usage

    /* Scenario: Set HFCLK0 divider to 8, to reduce frequency and save power */

    if(CY_SYSCLK_CLKHF_DIVIDE_BY_8 != Cy_SysClk_ClkHfGetDivider(0UL))
    {
        /* Set the HFCLK0 divider to 8 */
        (void)Cy_SysClk_ClkHfSetDivider(0UL, CY_SYSCLK_CLKHF_DIVIDE_BY_8);
    }

    /* Check the HFCLK0 frequency */
    uint32_t clkHf0freq = Cy_SysClk_ClkHfGetFrequency(0UL);

Parameters

clkHf – Selects the clkHf

Returns

The frequency, in Hz.

void Cy_SysClk_ClkFastSetDivider(uint8_t divider)

Sets the clock divider for the fast clock, which sources the main processor.

The source of this divider is clkHf[0].

note

Call SystemCoreClockUpdate after this function calling.

note

Call Cy_SysLib_SetWaitStates before calling this function if CLK_FAST frequency is increasing.

note

Call Cy_SysLib_SetWaitStates after calling this function if CLK_FAST frequency is decreasing.

Function Usage

    /* Scenario: HFCLK0 is configured and enabled. The Fast clock sourcing the
                 CM4 core must run at a frequency that is 1/16 of HFCLK0. */

    if(16u != Cy_SysClk_ClkFastGetDivider())
    {
        Cy_SysClk_ClkFastSetDivider(16u);
    }

    /* Get the CM4 clock source frequency */
    uint32_t clkFastfreq = Cy_SysClk_ClkFastGetFrequency();

Parameters

divider – divider value between 0 and 255. Causes integer division of (divider value + 1), or division by 1 to 256.

uint8_t Cy_SysClk_ClkFastGetDivider(void)

Returns the clock divider for the fast clock.

Function Usage

    /* Scenario: HFCLK0 is configured and enabled. The Fast clock sourcing the
                 CM4 core must run at a frequency that is 1/16 of HFCLK0. */

    if(16u != Cy_SysClk_ClkFastGetDivider())
    {
        Cy_SysClk_ClkFastSetDivider(16u);
    }

    /* Get the CM4 clock source frequency */
    uint32_t clkFastfreq = Cy_SysClk_ClkFastGetFrequency();

Returns

The divider value for the fast clock. The integer division done is by (divider value + 1), or division by 1 to 256.

uint32_t Cy_SysClk_ClkFastGetFrequency(void)

Reports the frequency of the fast clock.

Function Usage

    /* Scenario: HFCLK0 is configured and enabled. The Fast clock sourcing the
                 CM4 core must run at a frequency that is 1/16 of HFCLK0. */

    if(16u != Cy_SysClk_ClkFastGetDivider())
    {
        Cy_SysClk_ClkFastSetDivider(16u);
    }

    /* Get the CM4 clock source frequency */
    uint32_t clkFastfreq = Cy_SysClk_ClkFastGetFrequency();

Returns

The frequency, in Hz.

void Cy_SysClk_ClkPeriSetDivider(uint8_t divider)

Sets the clock divider for the peripheral clock tree.

All peripheral clock dividers are sourced from this clock. Also the Cortex M0+ clock divider is sourced from this clock. The source of this divider is clkHf[0]

note

Call SystemCoreClockUpdate after this function calling.

Function Usage

    /* Scenario: HFCLK0 is configured and enabled. The Peri clock sourcing the
                 majority of peripherals must run at a frequency that is 1/2
                 of HFCLK0. */

    if(1U != Cy_SysClk_ClkPeriGetDivider())
    {
        Cy_SysClk_ClkPeriSetDivider(1U);
    }

    /* Get the Peri clock output frequency */
    uint32_t clkPerifreq = Cy_SysClk_ClkPeriGetFrequency();

Parameters

divider – divider value between 0 and 255 Causes integer division of (divider value + 1), or division by 1 to 256.

uint32_t Cy_SysClk_ClkPeriGetFrequency(void)

Reports the frequency of the peri clock.

Function Usage

    /* Scenario: HFCLK0 is configured and enabled. The Peri clock sourcing the
                 majority of peripherals must run at a frequency that is 1/2
                 of HFCLK0. */

    if(1U != Cy_SysClk_ClkPeriGetDivider())
    {
        Cy_SysClk_ClkPeriSetDivider(1U);
    }

    /* Get the Peri clock output frequency */
    uint32_t clkPerifreq = Cy_SysClk_ClkPeriGetFrequency();

Returns

The frequency, in Hz.

uint8_t Cy_SysClk_ClkPeriGetDivider(void)

Returns the clock divider of the peripheral (peri) clock.

Function Usage

    /* Scenario: HFCLK0 is configured and enabled. The Peri clock sourcing the
                 majority of peripherals must run at a frequency that is 1/2
                 of HFCLK0. */

    if(1U != Cy_SysClk_ClkPeriGetDivider())
    {
        Cy_SysClk_ClkPeriSetDivider(1U);
    }

    /* Get the Peri clock output frequency */
    uint32_t clkPerifreq = Cy_SysClk_ClkPeriGetFrequency();

Returns

The divider value. The integer division done is by (divider value + 1), or division by 1 to 256.

cy_en_sysclk_status_t Cy_SysClk_PeriphSetDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum, uint32_t dividerValue)

Sets one of the programmable clock dividers.

This is only used for integer dividers. Use Cy_SysClk_PeriphSetFracDivider for setting factional dividers.

Precondition

If the specified clock divider is already enabled - it should be disabled prior to use this function by Cy_SysClk_PeriphDisableDivider.

Function Usage

    /* Scenario: 16-bit peripheral divider #2 needs to be incremented by 1. */

    uint32_t periDiv = Cy_SysClk_PeriphGetDivider(CY_SYSCLK_DIV_16_BIT, 2UL);
    (void)Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 2UL, periDiv + 1UL);

Parameters
  • dividerType – specifies which type of divider to use; cy_en_divider_types_t

  • dividerNum – the divider number.

  • dividerValue – divider value Causes integer division of (divider value + 1), or division by 1 to 256 (8-bit divider) or 1 to 65536 (16-bit divider).

Returns

cy_en_sysclk_status_t

uint32_t Cy_SysClk_PeriphGetDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum)

Returns the integer divider value for the specified divider.

One works for integer dividers. Use Cy_SysClk_PeriphGetFracDivider to get the fractional divider value

Function Usage

    /* Scenario: 16-bit peripheral divider #2 needs to be incremented by 1. */

    uint32_t periDiv = Cy_SysClk_PeriphGetDivider(CY_SYSCLK_DIV_16_BIT, 2UL);
    (void)Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 2UL, periDiv + 1UL);

Parameters
  • dividerType – specifies which type of divider to use; cy_en_divider_types_t

  • dividerNum – specifies which divider of the selected type to configure

Returns

The divider value. The integer division done is by (divider value + 1), or division by 1 to 256 (8-bit divider) or 1 to 65536 (16-bit divider).

cy_en_sysclk_status_t Cy_SysClk_PeriphSetFracDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum, uint32_t dividerIntValue, uint32_t dividerFracValue)

Sets one of the programmable clock dividers.

This function should only be used for fractional clock dividers.

Precondition

If the specified clock divider is already enabled - it should be disabled prior to use this function by Cy_SysClk_PeriphDisableDivider.

Function Usage

    /* Scenario: 16-bit fractional peripheral divider #0 needs to increment its
                 fractional value by 2. */

    uint32_t divIntVal, divFracVal;

    Cy_SysClk_PeriphGetFracDivider(CY_SYSCLK_DIV_16_5_BIT, 0UL, &divIntVal, &divFracVal);
    (void)Cy_SysClk_PeriphSetFracDivider(CY_SYSCLK_DIV_16_5_BIT, 0UL, divIntVal, divFracVal + 2UL);

Parameters
  • dividerType – specifies which type of divider to use; cy_en_divider_types_t

  • dividerNum – specifies which divider of the selected type to configure

  • dividerIntValue – the integer divider value The source of the divider is peri_clk, which is a divided version of hf_clk[0]. The divider value causes integer division of (divider value + 1), or division by 1 to 65536 (16-bit divider) or 1 to 16777216 (24-bit divider).

  • dividerFracValue – the fraction part of the divider The fractional divider can be 1-32, thus it divides the clock by 1/32 for each count. To divide the clock by 11/32nds set this value to 11.

Returns

cy_en_sysclk_status_t

void Cy_SysClk_PeriphGetFracDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum, uint32_t *dividerIntValue, uint32_t *dividerFracValue)

Reports the integer and fractional parts of the divider.

Function Usage

    /* Scenario: 16-bit fractional peripheral divider #0 needs to increment its
                 fractional value by 2. */

    uint32_t divIntVal, divFracVal;

    Cy_SysClk_PeriphGetFracDivider(CY_SYSCLK_DIV_16_5_BIT, 0UL, &divIntVal, &divFracVal);
    (void)Cy_SysClk_PeriphSetFracDivider(CY_SYSCLK_DIV_16_5_BIT, 0UL, divIntVal, divFracVal + 2UL);

Parameters
  • dividerType – specifies which type of divider to use; cy_en_divider_types_t

  • dividerNum – specifies which divider of the selected type to configure

  • *dividerIntValue – pointer to return integer divider value

  • *dividerFracValue – pointer to return fractional divider value

Returns

None. Loads pointed-to variables.

cy_en_sysclk_status_t Cy_SysClk_PeriphAssignDivider(en_clk_dst_t ipBlock, cy_en_divider_types_t dividerType, uint32_t dividerNum)

Assigns a programmable divider to a selected IP block, such as a TCPWM or SCB.

Function Usage

    /* Scenario: The source of TCPWM0 CNT0 clock needs to be known. If this
                 source is not 16-bit divider #3, update it to be sourced from
                 that clock divider and set the divider value to 2000. */

    uint32_t currDiv    = Cy_SysClk_PeriphGetAssignedDivider(PCLK_TCPWM0_CLOCKS0);
    uint32_t newDiv     = _VAL2FLD(PERI_DIV_CMD_TYPE_SEL, CY_SYSCLK_DIV_16_BIT)
                            | _VAL2FLD(PERI_DIV_CMD_DIV_SEL, 3UL);
    if(currDiv != newDiv)
    {
        /* Assign 16-bit divider #3 to source TCPWM0 CNT0 clock */
        (void)Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM0_CLOCKS0, CY_SYSCLK_DIV_16_BIT, 3UL);
    }

    /* Set the 16-bit divider #3 value to 2000 (1999 + 1) */
    (void)Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 3UL, 1999UL);

    /* Enable the 16-bit divider #3 */
    (void)Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 3UL);

Parameters
  • ipBlock – specifies ip block to connect the clock divider to.

  • dividerType – specifies which type of divider to use; cy_en_divider_types_t

  • dividerNum – specifies which divider of the selected type to configure

Returns

cy_en_sysclk_status_t

uint32_t Cy_SysClk_PeriphGetAssignedDivider(en_clk_dst_t ipBlock)

Reports which clock divider is assigned to a selected IP block.

Function Usage

    /* Scenario: The source of TCPWM0 CNT0 clock needs to be known. If this
                 source is not 16-bit divider #3, update it to be sourced from
                 that clock divider and set the divider value to 2000. */

    uint32_t currDiv    = Cy_SysClk_PeriphGetAssignedDivider(PCLK_TCPWM0_CLOCKS0);
    uint32_t newDiv     = _VAL2FLD(PERI_DIV_CMD_TYPE_SEL, CY_SYSCLK_DIV_16_BIT)
                            | _VAL2FLD(PERI_DIV_CMD_DIV_SEL, 3UL);
    if(currDiv != newDiv)
    {
        /* Assign 16-bit divider #3 to source TCPWM0 CNT0 clock */
        (void)Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM0_CLOCKS0, CY_SYSCLK_DIV_16_BIT, 3UL);
    }

    /* Set the 16-bit divider #3 value to 2000 (1999 + 1) */
    (void)Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 3UL, 1999UL);

    /* Enable the 16-bit divider #3 */
    (void)Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 3UL);

Parameters

ipBlock – specifies ip block to connect the clock divider to.

Returns

The divider type and number, where bits [7:6] = type, bits[5:0] = divider number within that type

cy_en_sysclk_status_t Cy_SysClk_PeriphEnableDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum)

Enables the selected divider.

note

This function also sets the phase alignment bits such that the enabled divider is aligned to clk_peri. See Cy_SysClk_PeriphDisableDivider() for information on how to phase-align a divider after it is enabled.

Function Usage

    /* Scenario: TCPWM0 CNT0 clock needs to be sourced from 8-bit divider #1 with
                 a value of 140. This clock must be aligned to Peri clock. */

    /* Assign 8-bit divider #1 to source TCPWM0 CNT0 clock */
    (void)Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM0_CLOCKS0, CY_SYSCLK_DIV_8_BIT, 1UL);

    /* Set the 8-bit divider #1 value to 140 (139 + 1) */
    (void)Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1UL, 139UL);

    /* Enable the 8-bit divider #1 */
    (void)Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1UL);

Parameters
  • dividerType – specifies which type of divider to use; cy_en_divider_types_t

  • dividerNum – specifies which divider of the selected type to configure

cy_en_sysclk_status_t Cy_SysClk_PeriphDisableDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum)

Disables a selected divider.

Function Usage

    /* Scenario: 8-bit divider #1 is no longer needed and can be disabled. */
    (void)Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1UL);

Parameters
  • dividerType – specifies which type of divider to use; cy_en_divider_types_t.

  • dividerNum – specifies which divider of the selected type to configure.

cy_en_sysclk_status_t Cy_SysClk_PeriphEnablePhaseAlignDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum, cy_en_divider_types_t dividerTypePA, uint32_t dividerNumPA)

First disables a selected divider (Cy_SysClk_PeriphDisableDivider), then aligns that divider to another programmable divider, and enables the selected divider.

The divider to align to must already be enabled in order to align a divider to it.

note

To phase-align a divider to clk_peri, set dividerTypePA to 3 and dividerNumPA to 63.

Function Usage

    /* Scenario: 8-bit divider #1 needs to be aligned to 16-bit divider #0. */

    /* Set the 8-bit divider #1 value to 125 (124 + 1) */
    (void)Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1UL, 124UL);
    (void)Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1UL);

    /* Set the 16-bit divider #0 value to 2000 (1999 + 1) */
    (void)Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0UL, 1999UL);
    (void)Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0UL);

    /* Align the 8-bit divider #1 to the 16-bit divider #0 */
    (void)Cy_SysClk_PeriphEnablePhaseAlignDivider(CY_SYSCLK_DIV_8_BIT, 1UL, CY_SYSCLK_DIV_16_BIT, 0UL);

Parameters
  • dividerType – specifies which type of divider to use; cy_en_divider_types_t.

  • dividerNum – specifies which divider of the selected type to configure.

  • dividerTypePA – type of divider to phase-align to; cy_en_divider_types_t.

  • dividerNumPA – divider number of type specified to phase align to.

bool Cy_SysClk_PeriphGetDividerEnabled(cy_en_divider_types_t dividerType, uint32_t dividerNum)

Reports the enabled/disabled atate of the selected divider.

Function Usage

    /* Scenario: Check if the 16-bit divider #0 is enabled. If it is not, then
                 enable the divider. */

    if(true == Cy_SysClk_PeriphGetDividerEnabled(CY_SYSCLK_DIV_16_BIT, 0UL))
    {
        (void)Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0UL);
    }

Parameters
  • dividerType – specifies which type of divider to use; cy_en_divider_types_t.

  • dividerNum – specifies which divider of the selected type to configure.

Returns

The enabled/disabled state;

false = disabled

true = enabled

uint32_t Cy_SysClk_PeriphGetFrequency(cy_en_divider_types_t dividerType, uint32_t dividerNum)

Reports the frequency of the output of a given peripheral divider.

note

The reported frequency may be zero, which indicates unknown. This happens if the source input is dsi_out or clk_altlf.

Function Usage

    /* Scenario: SCB0 needs to be clocked at PeriClk/3. Need to confirm that the
                 set frequency on the chosen peripheral divider is correct.
                 HFCLK0 and the clocks leading up it are configured. */

    /* Set the Peri clock divider to 2 (1 + 1) */
    Cy_SysClk_ClkPeriSetDivider(1U);

    /* Assign 8-bit divider #0 to source SCB0 clock */
    (void)Cy_SysClk_PeriphAssignDivider(PCLK_SCB0_CLOCK, CY_SYSCLK_DIV_8_BIT, 0UL);

    /* Set the 8-bit divider #0 value to 3 (2 + 1) */
    (void)Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0UL, 2UL);

    /* Enable the 8-bit divider #0 */
    (void)Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0UL);

    /* Calculate the frequency seen at the output of 8-bit divider #0 */
    uint32_t scbFreq = Cy_SysClk_PeriphGetFrequency(CY_SYSCLK_DIV_8_BIT, 0UL);

    if(scbFreq == 0UL)
    {
        /* Could not calculate the frequency. Check that the clock source
           is correct and/or verify by enabling the SCB0. */
    }
    else
    {
        /* Check that the frequency is as expected. */
    }

Parameters
  • dividerType – specifies which type of divider to use; cy_en_divider_types_t

  • dividerNum – specifies which divider of the selected type to configure

Returns

The frequency, in Hz.

void Cy_SysClk_ClkSlowSetDivider(uint8_t divider)

Sets the clock divider for the slow clock.

The source of this clock is the peripheral clock (clkPeri), which is sourced from clkHf[0].

note

Call SystemCoreClockUpdate after this function calling.

Function Usage

    /* Scenario: HFCLK0 is configured and enabled. The Slow clock sourcing the
                 CM0+ core must run at a frequency that is 1/32 of HFCLK0. */

    /* Slow clock is sourced from Peri clock. Set the divider to 1 (freq = HFCLK0) */
    Cy_SysClk_ClkPeriSetDivider(1u);

    if(32u != Cy_SysClk_ClkSlowGetDivider())
    {
        Cy_SysClk_ClkSlowSetDivider(32u);
    }

    /* Get the CM0+ clock source frequency */
    uint32_t clkSlowfreq = Cy_SysClk_ClkSlowGetFrequency();

Parameters

divider – Divider value between 0 and 255. Causes integer division of (divider value + 1), or division by 1 to 256.

uint8_t Cy_SysClk_ClkSlowGetDivider(void)

Reports the divider value for the slow clock.

Function Usage

    /* Scenario: HFCLK0 is configured and enabled. The Slow clock sourcing the
                 CM0+ core must run at a frequency that is 1/32 of HFCLK0. */

    /* Slow clock is sourced from Peri clock. Set the divider to 1 (freq = HFCLK0) */
    Cy_SysClk_ClkPeriSetDivider(1u);

    if(32u != Cy_SysClk_ClkSlowGetDivider())
    {
        Cy_SysClk_ClkSlowSetDivider(32u);
    }

    /* Get the CM0+ clock source frequency */
    uint32_t clkSlowfreq = Cy_SysClk_ClkSlowGetFrequency();

Returns

The divider value. The integer division done is by (divider value + 1), or division by 1 to 256.

uint32_t Cy_SysClk_ClkSlowGetFrequency(void)

Reports the frequency of the slow clock.

Function Usage

    /* Scenario: HFCLK0 is configured and enabled. The Slow clock sourcing the
                 CM0+ core must run at a frequency that is 1/32 of HFCLK0. */

    /* Slow clock is sourced from Peri clock. Set the divider to 1 (freq = HFCLK0) */
    Cy_SysClk_ClkPeriSetDivider(1u);

    if(32u != Cy_SysClk_ClkSlowGetDivider())
    {
        Cy_SysClk_ClkSlowSetDivider(32u);
    }

    /* Get the CM0+ clock source frequency */
    uint32_t clkSlowfreq = Cy_SysClk_ClkSlowGetFrequency();

Returns

The frequency, in Hz.

void Cy_SysClk_ClkLfSetSource(cy_en_clklf_in_sources_t source)

Sets the source for the low frequency clock(clkLf).

note

The watchdog timer (WDT) must be unlocked before calling this function.

Function Usage

    /* Scenario: LFCLK source needs to be updated to the ILO. */

    if(CY_SYSCLK_CLKLF_IN_ILO != Cy_SysClk_ClkLfGetSource())
    {
        Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_ILO);
    }

Parameters

sourcecy_en_clklf_in_sources_t

cy_en_clklf_in_sources_t Cy_SysClk_ClkLfGetSource(void)

Reports the source for the low frequency clock (clkLf).

Function Usage

    /* Scenario: LFCLK source needs to be updated to the ILO. */

    if(CY_SYSCLK_CLKLF_IN_ILO != Cy_SysClk_ClkLfGetSource())
    {
        Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_ILO);
    }

Returns

cy_en_clklf_in_sources_t

void Cy_SysClk_ClkTimerSetSource(cy_en_clktimer_in_sources_t source)

Sets the source for the timer clock (clk_timer).

The timer clock can be used as a source for SYSTICK as an alternate clock and one or more of the energy profiler counters.

Function Usage

    /* Scenario: The timer clock source needs to be updated to HFCLK0. */

    if(CY_SYSCLK_CLKTIMER_IN_HF0_NODIV != Cy_SysClk_ClkTimerGetSource())
    {
        Cy_SysClk_ClkTimerSetSource(CY_SYSCLK_CLKTIMER_IN_HF0_NODIV);
    }

Parameters

sourcecy_en_clktimer_in_sources_t

cy_en_clktimer_in_sources_t Cy_SysClk_ClkTimerGetSource(void)

Reports the source for the timer clock (clk_timer).

Function Usage

    /* Scenario: The timer clock source needs to be updated to HFCLK0. */

    if(CY_SYSCLK_CLKTIMER_IN_HF0_NODIV != Cy_SysClk_ClkTimerGetSource())
    {
        Cy_SysClk_ClkTimerSetSource(CY_SYSCLK_CLKTIMER_IN_HF0_NODIV);
    }

Returns

cy_en_clktimer_in_sources_t

void Cy_SysClk_ClkTimerSetDivider(uint8_t divider)

Sets the divider for the timer clock (clk_timer).

note

Do not change the divider value while the timer clock is enabled.

Function Usage

    /* Scenario: The timer divider needs to be updated to 64. */

    if(63u != Cy_SysClk_ClkTimerGetDivider())
    {
        Cy_SysClk_ClkTimerSetDivider(63u); /* divider = value + 1 */
    }

Parameters

divider – Divider value; valid range is 0 to 255. Divides the selected source (Cy_SysClk_ClkTimerSetSource) by the (value + 1).

uint8_t Cy_SysClk_ClkTimerGetDivider(void)

Reports the divider value for the timer clock (clk_timer).

Function Usage

    /* Scenario: The timer divider needs to be updated to 64. */

    if(63u != Cy_SysClk_ClkTimerGetDivider())
    {
        Cy_SysClk_ClkTimerSetDivider(63u); /* divider = value + 1 */
    }

Returns

The divider value

void Cy_SysClk_ClkTimerEnable(void)

Enables the timer clock (clk_timer).

The timer clock can be used as a source for SYSTICK and one or more of the energy profiler counters.

Function Usage

    /* Scenario: Timer clock needs to operate at HFCLK/32. */

    Cy_SysClk_ClkTimerSetSource(CY_SYSCLK_CLKTIMER_IN_HF0_DIV8);
    Cy_SysClk_ClkTimerSetDivider(3u); /* divider = value + 1 */
    Cy_SysClk_ClkTimerEnable();

    /* Use the Timer clock as a source for the alternative ARM SysTick clock or
       for an Energy Profile counter clock. */

    /* In case if there is a need to get the timer clock frequency */
    uint32_t timerClkFreq = Cy_SysClk_ClkTimerGetFrequency();

bool Cy_SysClk_ClkTimerIsEnabled(void)

Reports the Enabled/Disabled status of the Timer.

note

This API is available for CAT1A devices.

Function Usage

    /* Scenario: Timer clock is no longer required and needs to be disabled.
                 All peripherals clocked using this source are disabled. */

    if (Cy_SysClk_ClkTimerIsEnabled())
    {
        Cy_SysClk_ClkTimerDisable();
    }

Returns

Boolean status of Timer: true - Enabled, false - Disabled.

void Cy_SysClk_ClkTimerDisable(void)

Disables the timer clock (clk_timer).

Function Usage

    /* Scenario: Timer clock is no longer required and needs to be disabled.
                 All peripherals clocked using this source are disabled. */

    if (Cy_SysClk_ClkTimerIsEnabled())
    {
        Cy_SysClk_ClkTimerDisable();
    }

uint32_t Cy_SysClk_ClkTimerGetFrequency(void)

Reports the frequency of the timer clock (clk_timer).

note

If the the timer clock is not enabled - a zero frequency is reported.

note

This API is available for CAT1A devices.

Function Usage

    /* Scenario: Timer clock needs to operate at HFCLK/32. */

    Cy_SysClk_ClkTimerSetSource(CY_SYSCLK_CLKTIMER_IN_HF0_DIV8);
    Cy_SysClk_ClkTimerSetDivider(3u); /* divider = value + 1 */
    Cy_SysClk_ClkTimerEnable();

    /* Use the Timer clock as a source for the alternative ARM SysTick clock or
       for an Energy Profile counter clock. */

    /* In case if there is a need to get the timer clock frequency */
    uint32_t timerClkFreq = Cy_SysClk_ClkTimerGetFrequency();

void Cy_SysClk_ClkPumpSetSource(cy_en_clkpump_in_sources_t source)

Sets the source for the pump clock (clk_pump).

The pump clock can be used for the analog pumps in the CTBm block.

note

Do not change the source while the pump clock is enabled.

Function Usage

    /* Scenario: The pump clock source needs to be updated to path 0 clock. */

    if(CY_SYSCLK_PUMP_IN_CLKPATH0 != Cy_SysClk_ClkPumpGetSource())
    {
        Cy_SysClk_ClkPumpSetSource(CY_SYSCLK_PUMP_IN_CLKPATH0);
    }

Parameters

sourcecy_en_clkpump_in_sources_t

cy_en_clkpump_in_sources_t Cy_SysClk_ClkPumpGetSource(void)

Reports the source for the pump clock (clk_pump).

Function Usage

    /* Scenario: The pump clock source needs to be updated to path 0 clock. */

    if(CY_SYSCLK_PUMP_IN_CLKPATH0 != Cy_SysClk_ClkPumpGetSource())
    {
        Cy_SysClk_ClkPumpSetSource(CY_SYSCLK_PUMP_IN_CLKPATH0);
    }

Returns

cy_en_clkpump_in_sources_t

void Cy_SysClk_ClkPumpSetDivider(cy_en_clkpump_divide_t divider)

Sets the divider of the pump clock (clk_pump).

note

Do not change the divider value while the pump clock is enabled.

Function Usage

    /* Scenario: The pump clock divider needs to be updated to 4. */

    if(CY_SYSCLK_PUMP_DIV_4 != Cy_SysClk_ClkPumpGetDivider())
    {
        Cy_SysClk_ClkPumpSetDivider(CY_SYSCLK_PUMP_DIV_4);
    }

Parameters

dividercy_en_clkpump_divide_t

cy_en_clkpump_divide_t Cy_SysClk_ClkPumpGetDivider(void)

Reports the divider value for the pump clock (clk_pump).

Function Usage

    /* Scenario: The pump clock divider needs to be updated to 4. */

    if(CY_SYSCLK_PUMP_DIV_4 != Cy_SysClk_ClkPumpGetDivider())
    {
        Cy_SysClk_ClkPumpSetDivider(CY_SYSCLK_PUMP_DIV_4);
    }

Returns

cy_en_clkpump_divide_t

void Cy_SysClk_ClkPumpEnable(void)

Enables the pump clock (clk_pump).

The pump clock can be used for the analog pumps in the CTBm block.

Function Usage

    /* Scenario: The Pump clock must be sourced from the Path 2 clock. The
                 frequency of the pump clock must be 1/16 of Path 2 clock. */

    Cy_SysClk_ClkPumpSetSource(CY_SYSCLK_PUMP_IN_CLKPATH2);
    Cy_SysClk_ClkPumpSetDivider(CY_SYSCLK_PUMP_DIV_16);
    Cy_SysClk_ClkPumpEnable();
    /* Use the pump clock as the source for CTB(m) blocks. */
    /* In case if there is a need to get the pump clock frequency */
    uint32_t pumpClkFreq = Cy_SysClk_ClkPumpGetFrequency();

bool Cy_SysClk_ClkPumpIsEnabled(void)

Reports the Enabled/Disabled status of the ClkPump.

note

This API is available for CAT1A devices.

Function Usage

    /* Scenario: Pump clock is no longer required and needs to be disabled.
                 All peripherals clocked using this source are disabled. */

    if (Cy_SysClk_ClkPumpIsEnabled())
    {
        Cy_SysClk_ClkPumpDisable();
    }

Returns

Boolean status of ClkPump: true - Enabled, false - Disabled.

void Cy_SysClk_ClkPumpDisable(void)

Disables the pump clock (clk_pump).

Function Usage

    /* Scenario: Pump clock is no longer required and needs to be disabled.
                 All peripherals clocked using this source are disabled. */

    if (Cy_SysClk_ClkPumpIsEnabled())
    {
        Cy_SysClk_ClkPumpDisable();
    }

uint32_t Cy_SysClk_ClkPumpGetFrequency(void)

Reports the frequency of the pump clock (clk_pump).

note

If the the pump clock is not enabled - a zero frequency is reported.

note

This API is available for CAT1A devices.

Function Usage

    /* Scenario: The Pump clock must be sourced from the Path 2 clock. The
                 frequency of the pump clock must be 1/16 of Path 2 clock. */

    Cy_SysClk_ClkPumpSetSource(CY_SYSCLK_PUMP_IN_CLKPATH2);
    Cy_SysClk_ClkPumpSetDivider(CY_SYSCLK_PUMP_DIV_16);
    Cy_SysClk_ClkPumpEnable();
    /* Use the pump clock as the source for CTB(m) blocks. */
    /* In case if there is a need to get the pump clock frequency */
    uint32_t pumpClkFreq = Cy_SysClk_ClkPumpGetFrequency();

void Cy_SysClk_ClkBakSetSource(cy_en_clkbak_in_sources_t source)

Sets the source for the backup domain clock (clk_bak).

note

clkLf is not available in all power modes. For this reason, WCO is the preferred source. If the WCO is routed through the clkLf multiplexer (see Cy_SysClk_ClkLfSetSource), select WCO directly - do not select clkLf.

Function Usage

    /* Scenario: Backup clock source needs to be updated to the WCO. */

    if(CY_SYSCLK_BAK_IN_WCO != Cy_SysClk_ClkBakGetSource())
    {
        Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_WCO);
    }

Parameters

sourcecy_en_clkbak_in_sources_t

cy_en_clkbak_in_sources_t Cy_SysClk_ClkBakGetSource(void)

Reports the source for the backup domain clock (clk_bak).

Function Usage

    /* Scenario: Backup clock source needs to be updated to the WCO. */

    if(CY_SYSCLK_BAK_IN_WCO != Cy_SysClk_ClkBakGetSource())
    {
        Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_WCO);
    }

Returns

cy_en_clkbak_in_sources_t

struct cy_stc_fll_manual_config_t
#include <>

Structure containing information for manual configuration of FLL.

Public Members

uint32_t fllMult

CLK_FLL_CONFIG register, FLL_MULT bits.

uint16_t refDiv

CLK_FLL_CONFIG2 register, FLL_REF_DIV bits.

cy_en_fll_cco_ranges_t ccoRange

CLK_FLL_CONFIG4 register, CCO_RANGE bits.

bool enableOutputDiv

CLK_FLL_CONFIG register, FLL_OUTPUT_DIV bit.

uint16_t lockTolerance

CLK_FLL_CONFIG2 register, LOCK_TOL bits.

uint8_t igain

CLK_FLL_CONFIG3 register, FLL_LF_IGAIN bits.

uint8_t pgain

CLK_FLL_CONFIG3 register, FLL_LF_PGAIN bits.

uint16_t settlingCount

CLK_FLL_CONFIG3 register, SETTLING_COUNT bits.

cy_en_fll_pll_output_mode_t outputMode

CLK_FLL_CONFIG3 register, BYPASS_SEL bits.

uint16_t cco_Freq

CLK_FLL_CONFIG4 register, CCO_FREQ bits.

struct cy_stc_pll_config_t
#include <>

Structure containing information for configuration of a PLL.

Public Members

uint32_t inputFreq

frequency of PLL source, in Hz

uint32_t outputFreq

frequency of PLL output, in Hz

bool lfMode

CLK_PLL_CONFIG register, PLL_LF_MODE bit.

cy_en_fll_pll_output_mode_t outputMode

CLK_PLL_CONFIG register, BYPASS_SEL bits.

struct cy_stc_pll_manual_config_t
#include <>

Structure containing information for manual configuration of a PLL.

Public Members

uint8_t feedbackDiv

CLK_PLL_CONFIG register, FEEDBACK_DIV (P) bits.

uint8_t referenceDiv

CLK_PLL_CONFIG register, REFERENCE_DIV (Q) bits.

uint8_t outputDiv

CLK_PLL_CONFIG register, OUTPUT_DIV bits.

bool lfMode

CLK_PLL_CONFIG register, PLL_LF_MODE bit.

cy_en_fll_pll_output_mode_t outputMode

CLK_PLL_CONFIG register, BYPASS_SEL bits.