cy_pra_cfg_8h¶

The header file of the PRA driver. The API is not intended to be used directly by the user application.

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Version: 2.20
Copyright: Copyright 2020 Cypress Semiconductor Corporation SPDX-License-Identifier: Apache-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Functions

cy_en_pra_status_t Cy_PRA_SystemConfig(const cy_stc_pra_system_config_t *devConfig)

Validates cy_stc_pra_system_config_t and applies the provided settings.

Function Usage

    /* Scenario: there is a need to be done in case then PDL is used
     * in standalone mode without Board Support Packages
     * (that uses Device Configurator utility to provide
     * GeneratedSource folder for the initial configuration
     * of the device).
     */
    cy_en_pra_status_t status = CY_PRA_STATUS_INVALID_PARAM;

    cy_stc_pra_system_config_t sysConfig =
    {
        .powerEnable=true,
        .ldoEnable=true,
        .pmicEnable=false,
        .vBackupVDDDEnable=true,
        .ulpEnable=false,
        .ecoEnable=false,
        .extClkEnable=false,
        .iloEnable=true,
        .wcoEnable=false,
        .fllEnable=false,
        .pll0Enable=false,
        .pll1Enable=false,
        .path0Enable=true,
        .path1Enable=false,
        .path2Enable=false,
        .path3Enable=false,
        .path4Enable=false,
        .path5Enable=false,
        .clkFastEnable=true,
        .clkPeriEnable=true,
        .clkSlowEnable=true,
        .clkHF0Enable=true,
        .clkHF1Enable=false,
        .clkHF2Enable=false,
        .clkHF3Enable=false,
        .clkHF4Enable=false,
        .clkHF5Enable=false,
        .clkPumpEnable=false,
        .clkLFEnable=true,
        .clkBakEnable=false,
        .clkTimerEnable=false,
        .clkAltSysTickEnable=false,
        .piloEnable=false,
        .clkAltHfEnable=false,
        .ldoVoltage=(cy_en_syspm_ldo_voltage_t)CY_SYSPM_LDO_VOLTAGE_LP,
        .buckVoltage=(cy_en_syspm_buck_voltage1_t)0,
        .pwrCurrentModeMin=false,
        .ecoFreqHz=0,
        .ecoLoad=0,
        .ecoEsr=0,
        .ecoDriveLevel=0,
        .ecoInPort=(GPIO_PRT_Type *)0x0,
        .ecoOutPort=(GPIO_PRT_Type *)0x0,
        .ecoInPinNum=0,
        .ecoOutPinNum=0,
        .extClkFreqHz=0,
        .extClkPort=(GPIO_PRT_Type *)0x0,
        .extClkPinNum=0,
        .extClkHsiom=(en_hsiom_sel_t)HSIOM_SEL_GPIO,
        .iloHibernateON=true,
        .bypassEnable=false,
        .wcoInPort=(GPIO_PRT_Type *)0x0,
        .wcoOutPort=(GPIO_PRT_Type *)0x0,
        .wcoInPinNum=0,
        .wcoOutPinNum=0,
        .fllOutFreqHz=0,
        .fllMult=0,
        .fllRefDiv=0,
        .fllCcoRange=(cy_en_fll_cco_ranges_t)CY_SYSCLK_FLL_CCO_RANGE0,
        .enableOutputDiv=false,
        .lockTolerance=0,
        .igain=0,
        .pgain=0,
        .settlingCount=0,
        .outputMode=(cy_en_fll_pll_output_mode_t)CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
        .ccoFreq=0,
        .pll0OutFreqHz=0,
        .pll0FeedbackDiv=0,
        .pll0ReferenceDiv=0,
        .pll0OutputDiv=0,
        .pll0LfMode=false,
        .pll0OutputMode=(cy_en_fll_pll_output_mode_t)CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
        .pll1OutFreqHz=0,
        .pll1FeedbackDiv=0,
        .pll1ReferenceDiv=0,
        .pll1OutputDiv=0,
        .pll1LfMode=false,
        .pll1OutputMode=(cy_en_fll_pll_output_mode_t)CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
        .path0Src=(cy_en_clkpath_in_sources_t)CY_SYSCLK_CLKPATH_IN_IMO,
        .path1Src=(cy_en_clkpath_in_sources_t)CY_SYSCLK_CLKPATH_IN_IMO,
        .path2Src=(cy_en_clkpath_in_sources_t)CY_SYSCLK_CLKPATH_IN_IMO,
        .path3Src=(cy_en_clkpath_in_sources_t)CY_SYSCLK_CLKPATH_IN_IMO,
        .path4Src=(cy_en_clkpath_in_sources_t)CY_SYSCLK_CLKPATH_IN_IMO,
        .path5Src=(cy_en_clkpath_in_sources_t)CY_SYSCLK_CLKPATH_IN_IMO,
        .clkFastDiv=0,
        .clkPeriDiv=0,
        .clkSlowDiv=0,
        .hf0Source=(cy_en_clkhf_in_sources_t)CY_SYSCLK_CLKHF_IN_CLKPATH0,
        .hf0Divider=(cy_en_clkhf_dividers_t)CY_SYSCLK_CLKHF_NO_DIVIDE,
        .hf0OutFreqMHz=8,
        .hf1Source=(cy_en_clkhf_in_sources_t)CY_SYSCLK_CLKHF_IN_CLKPATH0,
        .hf1Divider=(cy_en_clkhf_dividers_t)CY_SYSCLK_CLKHF_NO_DIVIDE,
        .hf1OutFreqMHz=0,
        .hf2Source=(cy_en_clkhf_in_sources_t)CY_SYSCLK_CLKHF_IN_CLKPATH0,
        .hf2Divider=(cy_en_clkhf_dividers_t)CY_SYSCLK_CLKHF_NO_DIVIDE,
        .hf2OutFreqMHz=0,
        .hf3Source=(cy_en_clkhf_in_sources_t)CY_SYSCLK_CLKHF_IN_CLKPATH0,
        .hf3Divider=(cy_en_clkhf_dividers_t)CY_SYSCLK_CLKHF_NO_DIVIDE,
        .hf3OutFreqMHz=0,
        .hf4Source=(cy_en_clkhf_in_sources_t)CY_SYSCLK_CLKHF_IN_CLKPATH0,
        .hf4Divider=(cy_en_clkhf_dividers_t)CY_SYSCLK_CLKHF_NO_DIVIDE,
        .hf4OutFreqMHz=0,
        .hf5Source=(cy_en_clkhf_in_sources_t)CY_SYSCLK_CLKHF_IN_CLKPATH0,
        .hf5Divider=(cy_en_clkhf_dividers_t)CY_SYSCLK_CLKHF_NO_DIVIDE,
        .hf5OutFreqMHz=0,
        .pumpSource=(cy_en_clkpump_in_sources_t)CY_SYSCLK_PUMP_IN_CLKPATH0,
        .pumpDivider=(cy_en_clkpump_divide_t)CY_SYSCLK_PUMP_NO_DIV,
        .clkLfSource=(cy_en_clklf_in_sources_t)CY_SYSCLK_CLKLF_IN_ILO,
        .clkBakSource=(cy_en_clkbak_in_sources_t)CY_SYSCLK_BAK_IN_WCO,
        .clkTimerSource=(cy_en_clktimer_in_sources_t)CY_SYSCLK_CLKTIMER_IN_IMO,
        .clkTimerDivider=0,
        .clkSrcAltSysTick =(cy_en_systick_clock_source_t)CY_SYSTICK_CLOCK_SOURCE_CLK_LF,
        .altHFcLoad=0,
        .altHFxtalStartUpTime=0,
        .altHFclkFreq=0,
        .altHFsysClkDiv=0,
        .altHFvoltageReg=0
    };

    status = CY_PRA_FUNCTION_CALL_RETURN_PARAM(CY_PRA_MSG_TYPE_SYS_CFG_FUNC,
                                               CY_PRA_FUNC_INIT_CYCFG_DEVICE,
                                               &sysConfig);

Parameters: devConfig – The device configuration structure initialized with Device Configurator.
Returns: cy_en_pra_status_t

uint32_t Cy_PRA_CalculateFLLOutFreq(const cy_stc_pra_system_config_t *devConfig)

Calculates and returns the FLL output frequency.

Parameters: devConfig – System Configuration Parameter
Returns: The FLL output frequency.

uint32_t Cy_PRA_CalculatePLLOutFreq(uint8_t pll, const cy_stc_pra_system_config_t *devConfig)

Calculates and returns the PLL output frequency.

Parameters

pll – PLL number
devConfig – System Configuration Parameter

Returns

The PLL output frequency.

struct cy_stc_pra_system_config_t¶

#include <>

System configuration structure.

Public Members

bool powerEnable¶: Power is enabled or disabled.

bool ldoEnable¶: Core Regulator.

bool pmicEnable¶: Power using external PMIC output.

bool vBackupVDDDEnable¶: vBackup source using VDD or Direct supply

bool ulpEnable¶: System Active Power mode is ULP.

bool ecoEnable¶: ECO Enable.

bool extClkEnable¶: EXTCLK Enable.

bool iloEnable¶: ILO Enable.

bool wcoEnable¶: WCO Enable.

bool fllEnable¶: FLL Enable.

bool pll0Enable¶: PLL0 Enable.

bool pll1Enable¶: PLL1 Enable.

bool path0Enable¶: PATH_MUX0 Enable.

bool path1Enable¶: PATH_MUX1 Enable.

bool path2Enable¶: PATH_MUX2 Enable.

bool path3Enable¶: PATH_MUX3 Enable.

bool path4Enable¶: PATH_MUX4 Enable.

bool path5Enable¶: PATH_MUX5 Enable.

bool clkFastEnable¶: CLKFAST Enable.

bool clkPeriEnable¶: CLKPERI Enable.

bool clkSlowEnable¶: CLKSLOW Enable.

bool clkHF0Enable¶: CLKHF0 Enable.

bool clkHF1Enable¶: CLKHF1 Enable.

bool clkHF2Enable¶: CLKHF2 Enable.

bool clkHF3Enable¶: CLKHF3 Enable.

bool clkHF4Enable¶: CLKHF4 Enable.

bool clkHF5Enable¶: CLKHF5 Enable.

bool clkPumpEnable¶: CLKPUMP Enable.

bool clkLFEnable¶: CLKLF Enable.

bool clkBakEnable¶: CLKBAK Enable.

bool clkTimerEnable¶: CLKTIMER Enable.

bool clkAltSysTickEnable¶: CLKALTSYSTICK Enable.

bool piloEnable¶: PILO Enable.

bool clkAltHfEnable¶: BLE ECO Clock Enable.

cy_en_syspm_ldo_voltage_t ldoVoltage¶: LDO Voltage (LP or ULP)

cy_en_syspm_buck_voltage1_t buckVoltage¶: Buck Voltage.

bool pwrCurrentModeMin¶: Minimum core regulator current mode.

uint32_t ecoFreqHz¶: ECO Frequency in Hz.

uint32_t ecoLoad¶: Parallel Load Capacitance (pF)

uint32_t ecoEsr¶: Equivalent series resistance (ohm)

uint32_t ecoDriveLevel¶: Drive Level (uW)

GPIO_PRT_Type *ecoInPort¶: ECO input port.

GPIO_PRT_Type *ecoOutPort¶: ECO output port.

uint32_t ecoInPinNum¶: ECO input pin number.

uint32_t ecoOutPinNum¶: ECO output pin number.

uint32_t extClkFreqHz¶: External clock frequency in Hz.

GPIO_PRT_Type *extClkPort¶: External connection port.

uint32_t extClkPinNum¶: External connection pin.

en_hsiom_sel_t extClkHsiom¶: IO mux value.

bool iloHibernateON¶: Run in Hibernate Mode.

bool bypassEnable¶: Clock port bypass to External sine wave or to normal crystal.

GPIO_PRT_Type *wcoInPort¶: WCO Input port.

GPIO_PRT_Type *wcoOutPort¶: WCO Output port.

uint32_t wcoInPinNum¶: WCO Input pin.

uint32_t wcoOutPinNum¶: WCO Output pin.

uint32_t fllOutFreqHz¶: FLL Output Frequency in Hz.

uint32_t fllMult¶: CLK_FLL_CONFIG register, FLL_MULT bits.

uint16_t fllRefDiv¶: CLK_FLL_CONFIG2 register, FLL_REF_DIV bits.

cy_en_fll_cco_ranges_t fllCcoRange¶: CLK_FLL_CONFIG4 register, CCO_RANGE bits.

bool enableOutputDiv¶: CLK_FLL_CONFIG register, FLL_OUTPUT_DIV bit.

uint16_t lockTolerance¶: CLK_FLL_CONFIG2 register, LOCK_TOL bits.

uint8_t igain¶: CLK_FLL_CONFIG3 register, FLL_LF_IGAIN bits.

uint8_t pgain¶: CLK_FLL_CONFIG3 register, FLL_LF_PGAIN bits.

uint16_t settlingCount¶: CLK_FLL_CONFIG3 register, SETTLING_COUNT bits.

cy_en_fll_pll_output_mode_t outputMode¶: CLK_FLL_CONFIG3 register, BYPASS_SEL bits.

uint16_t ccoFreq¶: CLK_FLL_CONFIG4 register, CCO_FREQ bits.

uint32_t pll0OutFreqHz¶: PLL0 output frequency in Hz.

uint8_t pll0FeedbackDiv¶: PLL0 CLK_PLL_CONFIG register, FEEDBACK_DIV (P) bits.

uint8_t pll0ReferenceDiv¶: PLL0 CLK_PLL_CONFIG register, REFERENCE_DIV (Q) bits.

uint8_t pll0OutputDiv¶: PLL0 CLK_PLL_CONFIG register, OUTPUT_DIV bits.

bool pll0LfMode¶: PLL0 CLK_PLL_CONFIG register, PLL_LF_MODE bit.

cy_en_fll_pll_output_mode_t pll0OutputMode¶: PLL0 CLK_PLL_CONFIG register, BYPASS_SEL bits.

uint32_t pll1OutFreqHz¶: PLL1 output frequency in Hz.

uint8_t pll1FeedbackDiv¶: PLL1 CLK_PLL_CONFIG register, FEEDBACK_DIV (P) bits.

uint8_t pll1ReferenceDiv¶: PLL1 CLK_PLL_CONFIG register, REFERENCE_DIV (Q) bits.

uint8_t pll1OutputDiv¶: PLL1 CLK_PLL_CONFIG register, OUTPUT_DIV bits.

bool pll1LfMode¶: PLL1 CLK_PLL_CONFIG register, PLL_LF_MODE bit.

cy_en_fll_pll_output_mode_t pll1OutputMode¶: PLL1 CLK_PLL_CONFIG register, BYPASS_SEL bits.

cy_en_clkpath_in_sources_t path0Src¶: Input multiplexer0 clock source.

cy_en_clkpath_in_sources_t path1Src¶: Input multiplexer1 clock source.

cy_en_clkpath_in_sources_t path2Src¶: Input multiplexer2 clock source.

cy_en_clkpath_in_sources_t path3Src¶: Input multiplexer3 clock source.

cy_en_clkpath_in_sources_t path4Src¶: Input multiplexer4 clock source.

cy_en_clkpath_in_sources_t path5Src¶: Input multiplexer5 clock source.

uint8_t clkFastDiv¶

Fast clock divider.

User has to pass actual divider-1

uint8_t clkPeriDiv¶

Peri clock divider.

User has to pass actual divider-1

uint8_t clkSlowDiv¶

Slow clock divider.

User has to pass actual divider-1

cy_en_clkhf_in_sources_t hf0Source¶: HF0 Source Clock Path.

cy_en_clkhf_dividers_t hf0Divider¶: HF0 Divider.

uint32_t hf0OutFreqMHz¶: HF0 Output Frequency in MHz.

cy_en_clkhf_in_sources_t hf1Source¶: HF1 Source Clock Path.

cy_en_clkhf_dividers_t hf1Divider¶: HF1 Divider.

uint32_t hf1OutFreqMHz¶: HF1 Output Frequency in MHz.

cy_en_clkhf_in_sources_t hf2Source¶: HF2 Source Clock Path.

cy_en_clkhf_dividers_t hf2Divider¶: HF2 Divider.

uint32_t hf2OutFreqMHz¶: HF2 Output Frequency in MHz.

cy_en_clkhf_in_sources_t hf3Source¶: HF3 Source Clock Path.

cy_en_clkhf_dividers_t hf3Divider¶: HF3 Divider.

uint32_t hf3OutFreqMHz¶: HF3 Output Frequency in MHz.

cy_en_clkhf_in_sources_t hf4Source¶: HF4 Source Clock Path.

cy_en_clkhf_dividers_t hf4Divider¶: HF4 Divider.

uint32_t hf4OutFreqMHz¶: HF4 Output Frequency in MHz.

cy_en_clkhf_in_sources_t hf5Source¶: HF5 Source Clock Path.

cy_en_clkhf_dividers_t hf5Divider¶: HF5 Divider.

uint32_t hf5OutFreqMHz¶: HF5 Output Frequency in MHz.

cy_en_clkpump_in_sources_t pumpSource¶: PUMP Source Clock Path.

cy_en_clkpump_divide_t pumpDivider¶: PUMP Divider.

cy_en_clklf_in_sources_t clkLfSource¶: Clock LF Source.

cy_en_clkbak_in_sources_t clkBakSource¶: Clock Backup domain Source.

cy_en_clktimer_in_sources_t clkTimerSource¶: Clock Timer Source.

uint8_t clkTimerDivider¶: Clock Timer Divider.

cy_en_systick_clock_source_t clkSrcAltSysTick¶: SysTick Source.

uint32_t altHFcLoad¶: Load Cap (pF)

uint32_t altHFxtalStartUpTime¶: Startup Time (us)

uint32_t altHFclkFreq¶

Clock Frequency.

0 -> 16MHz and 1 -> 32MHz. Any other value except 0 and 1 is invalid

uint32_t altHFsysClkDiv¶: Clock Divider.

uint32_t altHFvoltageReg¶: BLE Voltage Regulator.