cy_i2s_8h¶

The header file of the I2S driver.

Version: 2.20

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Copyright: Copyright 2016-2020 Cypress Semiconductor Corporation SPDX-License-Identifier: Apache-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Defines

CY_I2S_DRV_VERSION_MAJOR¶: The driver major version.

CY_I2S_DRV_VERSION_MINOR¶: The driver minor version.

CY_I2S_ID¶: The I2S driver identifier.

CY_I2S_INTR_TX_TRIGGER¶: Bit 0: Less entries in the TX FIFO than specified by Trigger Level.

CY_I2S_INTR_TX_NOT_FULL¶: Bit 1: TX FIFO is not full.

CY_I2S_INTR_TX_EMPTY¶

Bit 4: TX FIFO is empty, i.e.

it has 0 entries.

CY_I2S_INTR_TX_OVERFLOW¶: Bit 5: Attempt to write to a full TX FIFO.

CY_I2S_INTR_TX_UNDERFLOW¶

Bit 6: Attempt to read from an empty TX FIFO.

This happens when the IP is ready to transfer data and TX_EMPTY is ‘1’.

CY_I2S_INTR_TX_WD¶: Bit 8: Tx watchdog event occurs.

CY_I2S_INTR_RX_TRIGGER¶: Bit 16: More entries in the RX FIFO than specified by Trigger Level.

CY_I2S_INTR_RX_NOT_EMPTY¶: Bit 18: RX FIFO is not empty.

CY_I2S_INTR_RX_FULL¶: Bit 19: RX FIFO is full.

CY_I2S_INTR_RX_OVERFLOW¶: Bit 21: Attempt to write to a full RX FIFO.

CY_I2S_INTR_RX_UNDERFLOW¶: Bit 22: Attempt to read from an empty RX FIFO.

CY_I2S_INTR_RX_WD¶: Bit 24: Rx watchdog event occurs.

CY_I2S_TX_START¶: Transmission is active.

CY_I2S_TX_PAUSE¶: Transmission is paused.

CY_I2S_RX_START¶: Reception is active.

Enums

enum cy_en_i2s_status_t¶

cy_en_i2s_status_t: I2S status definitions.

Values:

enumerator CY_I2S_SUCCESS¶: Successful.

enumerator CY_I2S_BAD_PARAM¶: One or more invalid parameters.

enum cy_en_i2s_alignment_t¶

cy_en_i2s_alignment_t: I2S data alignment.

Values:

enumerator CY_I2S_LEFT_JUSTIFIED¶: Left justified.

enumerator CY_I2S_I2S_MODE¶: I2S mode.

enumerator CY_I2S_TDM_MODE_A¶: TDM mode A.

enumerator CY_I2S_TDM_MODE_B¶: TDM mode B.

enum cy_en_i2s_len_t¶

cy_en_i2s_len_t: I2S channel/word length.

Values:

enumerator CY_I2S_LEN8¶: Channel/word length: 8 bit.

enumerator CY_I2S_LEN16¶: Channel/Word length: 16 bit.

enumerator CY_I2S_LEN18¶: Channel/Word length: 18 bit.

enumerator CY_I2S_LEN20¶: Channel/Word length: 20 bit.

enumerator CY_I2S_LEN24¶: Channel/Word length: 24 bit.

enumerator CY_I2S_LEN32¶: Channel/Word length: 32 bit.

enum cy_en_i2s_overhead_t¶

cy_en_i2s_overhead_t: I2S TX overhead value.

Values:

enumerator CY_I2S_OVHDATA_ZERO¶: Fill overhead bits by zeroes.

enumerator CY_I2S_OVHDATA_ONE¶: Fill overhead bits by ones.

enum cy_en_i2s_ws_pw_t¶

cy_en_i2s_ws_pw_t: I2S WS pulse width.

Values:

enumerator CY_I2S_WS_ONE_SCK_CYCLE¶: WS pulse width is one SCK cycle.

enumerator CY_I2S_WS_ONE_CHANNEL_LENGTH¶: WS pulse width is one channel length.

Functions

cy_en_i2s_status_t Cy_I2S_Init(I2S_Type *base, cy_stc_i2s_config_t const *config)

Initializes the I2S module in accordance with a configuration structure.

Precondition

If the I2S module is initialized previously, the Cy_I2S_DeInit() must be called before calling this function.

Function Usage

    /* Scenario: Setup a duplex 16-bit I2S interface */
    
    const cy_stc_i2s_config_t config =
    {
        /* .txEnabled          */ true,
        /* .rxEnabled          */ true,
        /* .txDmaTrigger       */ false,
        /* .rxDmaTrigger       */ false,
        /* .clkDiv             */ 16U,
        /* .extClk             */ false,
        /* .txMasterMode       */ false,
        /* .txAlignment        */ CY_I2S_I2S_MODE,
        /* .txWsPulseWidth     */ CY_I2S_WS_ONE_CHANNEL_LENGTH,
        /* .txWatchdogEnable   */ false,
        /* .txWatchdogValue    */ 0xFFFFFFFFUL,
        /* .txSdoLatchingTime  */ false,
        /* .txSckoInversion    */ false,
        /* .txSckiInversion    */ false,
        /* .txChannels         */ 2U,
        /* .txChannelLength    */ CY_I2S_LEN16,
        /* .txWordLength       */ CY_I2S_LEN16,
        /* .txOverheadValue    */ CY_I2S_OVHDATA_ZERO,
        /* .txFifoTriggerLevel */ 0U, /* In this example the trigger isn't used */
        /* .rxMasterMode       */ true,
        /* .rxAlignment        */ CY_I2S_I2S_MODE,
        /* .rxWsPulseWidth     */ CY_I2S_WS_ONE_CHANNEL_LENGTH,
        /* .rxWatchdogEnable   */ false,
        /* .rxWatchdogValue    */ 0xFFFFFFFFUL,
        /* .rxSdiLatchingTime  */ false,
        /* .rxSckoInversion    */ false,
        /* .rxSckiInversion    */ false,
        /* .rxChannels         */ 2U,
        /* .rxChannelLength    */ CY_I2S_LEN16,
        /* .rxWordLength       */ CY_I2S_LEN16,
        /* .rxSignExtension    */ false,
        /* .rxFifoTriggerLevel */ 0U /* In this example the trigger isn't used */
    };
    
    if(CY_I2S_SUCCESS != Cy_I2S_Init (I2S0, &config))
    {
        /* Insert error handling */
    }
    
    /* Clear both FIFOs */
    Cy_I2S_ClearRxFifo (I2S0);
    Cy_I2S_ClearTxFifo (I2S0);
    /* Put at least one frame (may be empty) into the Tx FIFO - two data words for I2S format */
    Cy_I2S_WriteTxData (I2S0, 0UL);
    Cy_I2S_WriteTxData (I2S0, 0UL);
    /* Clear possible pending interrupts */
    Cy_I2S_ClearInterrupt (I2S0, CY_I2S_INTR_TX_EMPTY);
    /* Enable interrupts */
    Cy_I2S_SetInterruptMask (I2S0, CY_I2S_INTR_TX_EMPTY | CY_I2S_INTR_RX_FULL);
    /* Enable communication */
    Cy_I2S_EnableRx (I2S0);
    Cy_I2S_EnableTx (I2S0);

Parameters

base – The pointer to the I2S instance address.
config – The pointer to a configuration structure.

Returns

error / status code. See cy_en_i2s_status_t.

void Cy_I2S_DeInit(I2S_Type *base)

Uninitializes the I2S module (reverts default register values).

Function Usage

    /* Scenario: The I2S block is initialized/working and then no longer used or needs to be reset */
    Cy_I2S_DeInit (I2S0);

Parameters: base – The pointer to the I2S instance address.

cy_en_syspm_status_t Cy_I2S_DeepSleepCallback(cy_stc_syspm_callback_params_t const *callbackParams, cy_en_syspm_callback_mode_t mode)

This is a callback function to be used at the application layer to manage an I2S operation during the Deep Sleep cycle.

It stores the I2S state (Tx/Rx enabled/disabled/paused) into the context structure and stops the communication before entering into Deep Sleep power mode and restores the I2S state after waking up.

note

Use the cy_stc_i2s_context_t data type for definition of the *context element of the cy_stc_syspm_callback_params_t structure.

Function Usage

    /* Scenario: The I2S hardware must be suitably prepared to enter device Deep Sleep Mode.
    It must stop all communication before Deep Sleep Mode entry and continue communication upon Deep Sleep Mode exit. */
    
    /* Context structure for Cy_I2S_DeepSleepCallback */
    cy_stc_i2s_context_t i2sDeepSleepCallbackContext;

    /* Parameters structure for Cy_I2S_DeepSleepCallback */
    cy_stc_syspm_callback_params_t i2sDeepSleepCallbackParams = 
    {
        (void*) I2S0,
        (void*) &i2sDeepSleepCallbackContext
    };
    
    /* Initialization structure for Cy_I2S_DeepSleepCallback */
    cy_stc_syspm_callback_t i2sDeepSleepCallback = 
    {
        (Cy_SysPmCallback)&Cy_I2S_DeepSleepCallback,
        CY_SYSPM_DEEPSLEEP,
        /* Skip execution for CHECK_READY and CHECK_FAIL events */
        CY_SYSPM_SKIP_CHECK_READY | CY_SYSPM_SKIP_CHECK_FAIL,
        &i2sDeepSleepCallbackParams,
        NULL,
        NULL,
        0
    };
    
    /* Register the Cy_I2S_DeepSleepCallback */
    if (CY_SYSPM_SUCCESS != Cy_SysPm_RegisterCallback(&i2sDeepSleepCallback))
    {
        /* Insert error handling */
    }
    
    /* Enter chip Deep Sleep Mode using the SysPm driver API */

Parameters

callbackParams – - The pointer to the callback parameters structure, see cy_stc_syspm_callback_params_t.
mode – Callback mode, see cy_en_syspm_callback_mode_t

Returns

the SysPm callback status cy_en_syspm_status_t.

__STATIC_INLINE void Cy_I2S_EnableTx (I2S_Type *base)

Starts an I2S transmission.

Interrupt enabling (by the Cy_I2S_SetInterruptMask) is required after this function call, in case if any I2S interrupts are used in the application.

Precondition

Cy_I2S_Init() must be called before.

Function Usage

    /* Scenario: the I2S block is initialized to operate in TX mode 
       and its interrupt mask has been configured (if used). 
       The TX FIFOs are prepared and the block is ready to be enabled for TX communication.*/
    Cy_I2S_EnableTx (I2S0);

Parameters: base – The pointer to the I2S instance address.

__STATIC_INLINE void Cy_I2S_PauseTx (I2S_Type *base)

Pauses an I2S transmission.

Function Usage

    /* Scenario: The I2S transmission is running and there is a need be paused */
    Cy_I2S_PauseTx (I2S0);

Parameters: base – The pointer to the I2S instance address.

__STATIC_INLINE void Cy_I2S_ResumeTx (I2S_Type *base)

Resumes an I2S transmission.

Function Usage

    /* Scenario: The I2S transmission is paused and there is a need be resumed */
    Cy_I2S_ResumeTx (I2S0);    

Parameters: base – The pointer to the I2S instance address.

__STATIC_INLINE void Cy_I2S_DisableTx (I2S_Type *base)

Stops an I2S transmission.

Precondition

TX interrupt disabling (by the Cy_I2S_SetInterruptMask) is required prior to this function call, in case any TX I2S interrupts are used.

Function Usage

    /* Scenario: The I2S transmission is running and no longer required
       so needs to be turned off. */
    Cy_I2S_DisableTx (I2S0);
    /* Disable all the TX interrupts here */

Parameters: base – The pointer to the I2S instance address.

__STATIC_INLINE void Cy_I2S_EnableRx (I2S_Type *base)

Starts an I2S reception.

Interrupt enabling (by the Cy_I2S_SetInterruptMask) is required after this function call, in case any I2S interrupts are used in the application.

Precondition

Cy_I2S_Init() must be called before.

Function Usage

    /* Scenario: The I2S block is initialized to operate in RX mode 
       and its interrupt mask has been configured (if used).
       The RX FIFO is cleared and ready for data reception. */
    Cy_I2S_EnableRx (I2S0);

Parameters: base – The pointer to the I2S instance address.

__STATIC_INLINE void Cy_I2S_DisableRx (I2S_Type *base)

Stops an I2S reception.

Precondition

RX interrupt disabling (by the Cy_I2S_SetInterruptMask) is required prior to this function call, in case any RX I2S interrupts are used.

Function Usage

    /* Scenario: The I2S reception is running and no longer required
       so needs to be turned off. */
    Cy_I2S_DisableRx (I2S0);

Parameters: base – The pointer to the I2S instance address.

__STATIC_INLINE uint32_t Cy_I2S_GetCurrentState (I2S_Type const *base)

Returns the current I2S state (TX/RX running/paused/stopped).

Function Usage

    /* Scenario: Need to check whether the I2S transmission is running */
    uint32_t state = Cy_I2S_GetCurrentState(I2S0);
    if ((0UL != (CY_I2S_TX_START & state)) &&
        (0UL == (CY_I2S_TX_PAUSE & state)))
    {
        /* The I2S transmission is running (enabled and not paused) */
    }

Parameters: base – The pointer to the I2S instance address.
Returns: The current state Current State.

__STATIC_INLINE void Cy_I2S_ClearTxFifo (I2S_Type *base)

Clears the TX FIFO (resets the Read/Write FIFO pointers).

Function Usage

    /* Scenario: Empty the contents of the TX FIFO in preparation for a new set of TX data */
    Cy_I2S_ClearTxFifo(I2S0);

Parameters: base – The pointer to the I2S instance address.

__STATIC_INLINE uint32_t Cy_I2S_GetNumInTxFifo (I2S_Type const *base)

Gets the number of used words in the TX FIFO.

Function Usage

    /* Scenario: New data set needs to be loaded into the TX buffer.
       However first check the number of data words currently in the TX FIFO. */
    if (254UL > Cy_I2S_GetNumInTxFifo(I2S0))
    {
        /* There are more than 2 empty words in the TX FIFO, 
           so load the next I2S frame using Cy_I2S_WriteTxData */
    }

Parameters: base – The pointer to the I2S instance address.
Returns: The current number of used words in the TX FIFO.

__STATIC_INLINE void Cy_I2S_WriteTxData (I2S_Type *base, uint32_t data)

Writes data to the TX FIFO.

Increases the TX FIFO level.

Function Usage

    Cy_I2S_WriteTxData(I2S0, 1UL); /* The last word in the Tx FIFO is 0x00000001. */
    Cy_I2S_WriteTxData(I2S0, 2UL); /* Now the last word in the Tx FIFO is 0x00000002,
                                     and previous is 0x00000001. */

Parameters

base – The pointer to the I2S instance address.
data – Data to be written to the TX FIFO.

__STATIC_INLINE uint8_t Cy_I2S_GetTxReadPointer (I2S_Type const *base)

Gets the TX FIFO Read pointer.

This function is for debug purposes.

Function Usage

    /* Scenario: Need to check the Tx FIFO read pointer */
    uint8_t readPointer = Cy_I2S_GetTxReadPointer(I2S0);
    /* readPointer now contains the read pointer of the Tx FIFO.
       The Tx FIFO read pointer increments when transmission is enabled and 
       HW takes a data word from FIFO into the transmitter */

Parameters: base – The pointer to the I2S instance address.
Returns: The current TX Read pointer value.

__STATIC_INLINE uint8_t Cy_I2S_GetTxWritePointer (I2S_Type const *base)

Gets the TX FIFO Write pointer.

This function is for debug purposes.

Function Usage

    /* Scenario: Need to check the Tx FIFO write pointer */
    uint8_t writePointer = Cy_I2S_GetTxWritePointer(I2S0);
    /* writePointer now contains the write pointer of the Tx FIFO.
       The Tx FIFO write pointer increments when a data word is written into the
       FIFO by \ref Cy_I2S_WriteTxData. */

Parameters: base – The pointer to the I2S instance address.
Returns: The current TX Write pointer value.

__STATIC_INLINE void Cy_I2S_FreezeTxFifo (I2S_Type *base)

Freezes the TX FIFO.

This function is for debug purposes.

Function Usage

    /* Scenario: Need to freeze the Tx FIFO for debugging purposes */
    Cy_I2S_FreezeTxFifo(I2S0);
    /* Now the read pointer of the Tx FIFO will be not affected by HW. */

Parameters: base – The pointer to the I2S instance address.

__STATIC_INLINE void Cy_I2S_UnfreezeTxFifo (I2S_Type *base)

Unfreezes the TX FIFO.

This function is for debug purposes.

Function Usage

    /* Scenario: The Tx FIFO was previously frozen and now needs to be unfrozen */
    Cy_I2S_UnfreezeTxFifo(I2S0);
    /* Now the Tx FIFO works as usually. */

Parameters: base – The pointer to the I2S instance address.

__STATIC_INLINE void Cy_I2S_ClearRxFifo (I2S_Type *base)

Clears the RX FIFO (resets the Read/Write FIFO pointers).

Function Usage

    /* Scenario: Empty the contents of the RX FIFO in preparation for a new data reception */
    Cy_I2S_ClearRxFifo(I2S0);

Parameters: base – The pointer to the I2S instance address.

__STATIC_INLINE uint32_t Cy_I2S_GetNumInRxFifo (I2S_Type const *base)

Gets the number of used words in the RX FIFO.

Function Usage

    /* Scenario: Waiting for new received data, check how many data words are in the Rx FIFO  */
    if (2UL < Cy_I2S_GetNumInRxFifo(I2S0))
    {
        /* There are more than 2 data words in the RX FIFO, 
           so get them using Cy_I2S_ReadRxData */
    }

Parameters: base – The pointer to the I2S instance address.
Returns: The current number of used words in rge RX FIFO.

__STATIC_INLINE uint32_t Cy_I2S_ReadRxData (I2S_Type const *base)

Reads data from the RX FIFO.

Decreases the RX FIFO level.

Function Usage

    /* Scenario: Need to get two data words from the Rx FIFO */
    uint32_t data[2];
    data[0] = Cy_I2S_ReadRxData(I2S0); /* The data[0] contains the first word from the Rx FIFO */
    data[1] = Cy_I2S_ReadRxData(I2S0); /* The data[1] contains the next word 
                                            (which is actually the first now) from the Rx FIFO */

Parameters: base – The pointer to the I2S instance address.
Returns: The read data.

__STATIC_INLINE uint32_t Cy_I2S_ReadRxDataSilent (I2S_Type const *base)

Reads data from the RX FIFO without updating the RX FIFO read pointer.

This function is for debug purposes.

Function Usage

    /* Scenario: Need to get a data silently from the Rx FIFO (don't increment FIFO read pointer) */
    uint32_t data[4];
    data[0] = Cy_I2S_ReadRxDataSilent(I2S0); /* The data[0] contains the first word from the Rx FIFO */
    data[1] = Cy_I2S_ReadRxDataSilent(I2S0); /* The data[1] contains the same first word from the Rx FIFO */
    data[2] = Cy_I2S_ReadRxData(I2S0); /* The data[2] contains the same first word from the Rx FIFO */
    data[3] = Cy_I2S_ReadRxData(I2S0); /* The data[3] contains the next (the first now) word from the Rx FIFO */

Parameters: base – The pointer to the I2S instance address.
Returns: The read data.

__STATIC_INLINE uint8_t Cy_I2S_GetRxReadPointer (I2S_Type const *base)

Gets the RX FIFO Read pointer.

This function is for debug purposes.

Function Usage

    /* Scenario: Need to check the Rx FIFO read pointer */
    uint8_t readPointer = Cy_I2S_GetRxReadPointer(I2S0);
    /* readPointer now contains the read pointer of the Rx FIFO.
       The Rx FIFO read pointer increments when a data word is read from the
       FIFO by \ref Cy_I2S_ReadRxData. */

Parameters: base – The pointer to the I2S instance address.
Returns: The current RX Read pointer value.

__STATIC_INLINE uint8_t Cy_I2S_GetRxWritePointer (I2S_Type const *base)

Gets the RX FIFO Write pointer.

This function is for debug purposes.

Function Usage

    /* Scenario: Need to check the Rx FIFO write pointer */
    uint8_t writePointer = Cy_I2S_GetRxWritePointer(I2S0);
    /* writePointer now contains the write pointer of the Rx FIFO.
       The Rx FIFO write pointer increments when the I2S reception is running
       and HW drops a data word into the FIFO. */

Parameters: base – The pointer to the I2S instance address.
Returns: The current RX Write pointer value.

__STATIC_INLINE void Cy_I2S_FreezeRxFifo (I2S_Type *base)

Freezes the RX FIFO.

This function is for debug purposes.

Function Usage

    /* Scenario: Need to freeze the Rx FIFO */
    Cy_I2S_FreezeRxFifo(I2S0);
    /* Now the write pointer of the Rx FIFO will be not affected by HW. */

Parameters: base – The pointer to the I2S instance address.

__STATIC_INLINE void Cy_I2S_UnfreezeRxFifo (I2S_Type *base)

Unfreezes the RX FIFO.

This function is for debug purposes.

Function Usage

    /* Scenario: The Rx FIFO was previously frozen and now needs to be unfrozen */
    Cy_I2S_UnfreezeRxFifo(I2S0);
    /* Now the Rx FIFO works as usually. */

Parameters: base – The pointer to the I2S instance address.

__STATIC_INLINE uint32_t Cy_I2S_GetInterruptStatus (I2S_Type const *base)

Gets an interrupt status (returns a content of the INTR register).

Function Usage

    /* Scenario: Need to check TX_EMPTY interrupt status regardless of whether it is enabled (masked) or not */
    if (0UL != (CY_I2S_INTR_TX_EMPTY & Cy_I2S_GetInterruptStatus (I2S0)))
    {
        /* The TX_EMPTY interrupt is pending */
    }

Parameters: base – The pointer to the I2S instance address.
Returns: The interrupt bit mask Interrupt Masks.

__STATIC_INLINE void Cy_I2S_ClearInterrupt (I2S_Type *base, uint32_t interrupt)

Clears one or more interrupt factors (sets the INTR register).

Function Usage

    /* Scenario: Inside the I2S interrupt service routine */

    /* Get all the enabled pending interrupts */
    uint32_t interrupt = Cy_I2S_GetInterruptStatusMasked (I2S0);

    if (0UL != (CY_I2S_INTR_TX_EMPTY & interrupt))
    {
        /* Handle the TX_EMPTY interrupt - fill the Tx FIFO, etc. */
    }

    /* Check and handle the rest of I2S interrupt types, if needed */

    /* Clear the interrupt */
    Cy_I2S_ClearInterrupt(I2S0, interrupt);

Parameters

base – The pointer to the I2S instance address.
interrupt – Interrupt bit mask Interrupt Masks.

__STATIC_INLINE void Cy_I2S_SetInterrupt (I2S_Type *base, uint32_t interrupt)

Sets one or more interrupt factors (sets the INTR_SET register).

Function Usage

    /* Scenario: Test the TX_EMPTY interrupt */
    Cy_I2S_SetInterrupt(I2S0, CY_I2S_INTR_TX_EMPTY); /* Set the TX_EMPTY by software */
    /* Now the TX_EMPTY interrupt should occur (if it is enabled, of course) */

Parameters

base – The pointer to the I2S instance address.
interrupt – Interrupt bit mask Interrupt Masks.

__STATIC_INLINE uint32_t Cy_I2S_GetInterruptMask (I2S_Type const *base)

Returns the interrupt mask (a content of the INTR_MASK register).

Function Usage

    /* Scenario: Need to enable the TX_EMPTY interrupt apart from all other interrupts */
    Cy_I2S_SetInterruptMask (I2S0, CY_I2S_INTR_TX_EMPTY | Cy_I2S_GetInterruptMask (I2S0));

Parameters: base – The pointer to the I2S instance address.
Returns: The interrupt bit mask Interrupt Masks.

__STATIC_INLINE void Cy_I2S_SetInterruptMask (I2S_Type *base, uint32_t interrupt)

Sets one or more interrupt factor masks (the INTR_MASK register).

Function Usage

    /* Scenario: Enable I2S interrupts (if any used) */
    Cy_I2S_SetInterruptMask (I2S0, CY_I2S_INTR_TX_TRIGGER   |
                                  CY_I2S_INTR_TX_NOT_FULL  |
                                  CY_I2S_INTR_TX_EMPTY     |
                                  CY_I2S_INTR_TX_OVERFLOW  |
                                  CY_I2S_INTR_TX_UNDERFLOW |
                                  CY_I2S_INTR_TX_WD        |
                                  CY_I2S_INTR_RX_TRIGGER   |
                                  CY_I2S_INTR_RX_NOT_EMPTY |
                                  CY_I2S_INTR_RX_FULL      |
                                  CY_I2S_INTR_RX_OVERFLOW  |
                                  CY_I2S_INTR_RX_UNDERFLOW |
                                  CY_I2S_INTR_RX_WD); /* Remove needless items */

    /* Scenario: Disable I2S interrupts (if any enabled) */
    Cy_I2S_SetInterruptMask (I2S0, 0UL); /* Disable all I2S interrupts */

Parameters

base – The pointer to the I2S instance address.
interrupt – Interrupt bit mask Interrupt Masks.

__STATIC_INLINE uint32_t Cy_I2S_GetInterruptStatusMasked (I2S_Type const *base)

Returns the interrupt status masked (a content of the INTR_MASKED register).

Function Usage

    /* Scenario: Inside the I2S interrupt service routine */

    /* Get all the enabled pending interrupts */
    uint32_t interrupt = Cy_I2S_GetInterruptStatusMasked (I2S0);

    if (0UL != (CY_I2S_INTR_TX_EMPTY & interrupt))
    {
        /* Handle the TX_EMPTY interrupt - fill the Tx FIFO, etc. */
    }

    /* Check and handle the rest of I2S interrupt types, if needed */

    /* Clear the interrupt */
    Cy_I2S_ClearInterrupt(I2S0, interrupt);

Parameters: base – The pointer to the I2S instance address.
Returns: The interrupt bit mask(s) Interrupt Masks.

struct cy_stc_i2s_config_t¶

#include <>

I2S initialization configuration.

Public Members

bool txEnabled¶

Enables the I2S TX component: ‘false’: disabled.

‘true’: enabled.

bool rxEnabled¶

Enables the I2S RX component: ‘false’: disabled.

‘true’: enabled.

bool txDmaTrigger¶: ‘false’: TX DMA trigger disabled, ‘true’: TX DMA trigger enabled.

bool rxDmaTrigger¶: ‘false’: RX DMA trigger disabled, ‘true’: RX DMA trigger enabled.

uint8_t clkDiv¶: CLK_SEL divider: 1: Bypass, 2: 1/2, 3: 1/3, …, 64: 1/64.

bool extClk¶: ‘false’: internal clock, ‘true’: external clock.

bool txMasterMode¶: ‘false’: TX in slave mode, ‘true’: TX in master mode.

cy_en_i2s_alignment_t txAlignment¶: TX data alignment, see: cy_en_i2s_alignment_t.

cy_en_i2s_ws_pw_t txWsPulseWidth¶

TX Word Select pulse width.

The value of this parameter is ignored in I2S and Left Justified modes the WS pulse width is always “one channel length” in these modes.

bool txWatchdogEnable¶: ‘false’: TX watchdog disabled, ‘true’: TX watchdog enabled.

uint32_t txWatchdogValue¶: TX watchdog counter value (32 bit).

bool txSdoLatchingTime¶

‘false’: SDO bit starts at falling edge (accordingly to the I2S Standard, if txSckoInversion is false), ‘true’: SDO bit starts at rising edge which goes before the above mentioned falling edge, i.e.

the SDO signal is advanced by 0.5 SCK period (if txSckoInversion is false). If txSckoInversion is true - the rising/falling edges just swaps in above explanations. Effective only in slave mode, must be false in master mode.

bool txSckoInversion¶

TX SCKO polarity: ‘false’: When transmitter is in master mode, serial data is transmitted off the falling bit clock edge (accordingly to the I2S Standard); ‘true’: When transmitter is in master mode, serial data is transmitted off the rising bit clock edge.

Effective only in master mode.

bool txSckiInversion¶

TX SCKI polarity: ‘false’: When transmitter is in slave mode, serial data is transmitted off the falling bit clock edge (accordingly to the I2S Standard); ‘true’: When transmitter is in slave mode, serial data is transmitted off the rising bit clock edge.

Effective only in slave mode.

uint8_t txChannels¶

Number of TX channels, valid range is 1…8 for TDM modes.

In the I2S and Left Justified modes the value of this parameter is ignored - the real number of channels is always 2 in these modes.

cy_en_i2s_len_t txChannelLength¶: TX channel length, see cy_en_i2s_len_t, the value of this parameter is ignored in TDM modes, the real channel length is 32 bit in these modes.

cy_en_i2s_len_t txWordLength¶: TX word length, see cy_en_i2s_len_t, must be less or equal to txChannelLength.

cy_en_i2s_overhead_t txOverheadValue¶: TX overhead bits value when the word length is less than the channel length.

uint8_t txFifoTriggerLevel¶: TX FIFO interrupt trigger level (0, 1, …, 255).

bool rxMasterMode¶: ‘false’: RX in slave mode, ‘true’: RX in master mode.

cy_en_i2s_alignment_t rxAlignment¶: RX data alignment, see: cy_en_i2s_alignment_t.

cy_en_i2s_ws_pw_t rxWsPulseWidth¶

RX Word Select pulse width.

The value of this parameter is ignored in I2S and Left Justified modes the WS pulse width is always “one channel length” in these modes.

bool rxWatchdogEnable¶: ‘false’: RX watchdog disabled, ‘true’: RX watchdog enabled.

uint32_t rxWatchdogValue¶: RX watchdog counter value (32 bit).

bool rxSdiLatchingTime¶

‘false’: SDI bit starts at falling edge (accordingly to the I2S Standard if rxSckoInversion is false), ‘true’: SDI bit starts at rising edge that goes after the above mentioned falling edge, i.e.

the SDI signal is delayed by 0.5 SCK period (if rxSckoInversion is false). If rxSckoInversion is true - the rising/falling edges just swaps in above explanations. Effective only in master mode, must be false in slave mode.

bool rxSckoInversion¶

RX SCKO polarity: ‘false’: When receiver is in master mode, serial data is captured by the rising bit clock edge (accordingly to the I2S Standard); ‘true’: When receiver is in master mode, serial data is captured by the falling bit clock edge.

Effective only in master mode.

bool rxSckiInversion¶

RX SCKI polarity: ‘false’: When receiver is in slave mode, serial data is captured by the rising bit clock edge (accordingly to the I2S Standard); ‘true’: When receiver is in slave mode, serial data is captured by the falling bit clock edge.

Effective only in slave mode.

uint8_t rxChannels¶

Number of RX channels, valid range is 1…8 for TDM modes.

In the I2S and Left Justified modes the value of this parameter is ignored - the real number of channels is always 2 in these modes.

cy_en_i2s_len_t rxChannelLength¶: RX channel length, see cy_en_i2s_len_t, the value of this parameter is ignored in TDM modes, the real channel length is 32 bit in these modes.

cy_en_i2s_len_t rxWordLength¶: RX word length, see cy_en_i2s_len_t, must be less or equal to rxChannelLength.

bool rxSignExtension¶: RX value sign extension (when the word length is less than 32 bits), ‘false’: all MSB are filled by zeroes, ‘true’: all MSB are filled by the original sign bit value.

uint8_t rxFifoTriggerLevel¶: RX FIFO interrupt trigger level (0, 1, …, (255 - (number of channels))).

struct cy_stc_i2s_context_t¶

#include <>

The I2S backup structure type to be used for the SysPm callback.

Cy_I2S_DeepSleepCallback context definition.

Public Members

uint32_t enableState¶: Stores the I2S state.

uint32_t interruptMask¶: Stores the I2S interrupt mask.